tag:blogger.com,1999:blog-16224711011836679182024-03-21T23:42:08.710-04:0029 Fully Differential Operational Amplifiers - conocimientos.com.veFully Differential Operational Amplifiers. Properties of Fully Differential Amplifiers. Small-Signal Models for Balanced Differential Amplifiers. Common-Mode Feedback. Common-Mode Feedback at Low Frequencies. Stability and Compensation Considerations in a CMFB Loop. CMFB Circuits. Fully Differential Op Amps. Unbalanced Fully Differential Circuits. Bandwidth of the CMFB Loop.Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.comBlogger88125tag:blogger.com,1999:blog-1622471101183667918.post-35312996884764068352010-07-26T00:06:00.003-04:302010-07-27T16:52:11.838-04:30A Continuous-Time Common-Mode Feedback Circuit (CMFB) for High-Impedance Current Mode Application<h3 class="post-title entry-title"><a href="http://indianamaithe.blogspot.com/2010/07/continuous-time-common-mode-feedback.html"></a> </h3><div class="post-header"></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"></span></span> <b style="color: #93c47d;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Abstract</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">A continuous-time common-mode feedback circuit (CMFB) is presented. A two-stage high-gain architecture is used to minimize the offset of the common-mode voltage. A special compensation scheme enables this circuit to be used in high-impedance current-mode systems without a stability problem. Simulation and testing results show the superior performance of this circuit. It is proven to be an ideal common-mode feedback circuit for systems which require an accurate and stable common mode voltage. This circuit has been implemented in a continuous-time switched-current Σ∆ modulator with a 2um CMOS process. With a 50MHz clock, the modulator has achieved a 60dB dynamic range in a 1MHz bandwidth.</span></span><br />
<br />
<b style="color: #93c47d;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">1. Introduction</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Common-mode feedback circuits (CMFB) stabilize common-mode voltages for fully-differential analog systems by means of adjusting the common-mode output currents. The two differential output voltages are averaged (VCM) and compared with the common-mode reference voltage (VRCM), and the differential voltage is converted to the common-mode output current to adjust the common-mode voltage (VCM). Three different techniques have been used for implementing CMFBs:</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">* Switched-capacitor</span></span><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">* Differential difference amplifier (DDA)</span></span><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">* Resistor-averaged circuit</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Suffering from clock-induced noise, switched capacitor common-mode feedback circuits are suitable only for sampled-data circuits [1][2]. Common-mode feedback circuits implemented by differential-difference amplifiers (DDA) use four identical transistors to average and compare the common-mode voltages [3]–[6]. Due to the limited input range and nonlinearity of the differential pairs, DDA CMFBs can work only for circuits with small voltage swing. The input range and linearity can be improved, however, by reducing the aspect ratios (W/L) of the CMOS transistors or increasing the bias current source. Resistor-averaged common-mode feedback circuits use resistors to average the two differential outputs and send the result to a differential pair to compare with VRCM [7][8]. This technique reduces the common-mode voltage error caused by the nonlinearity of the differential pair. The voltage swing ranges are not limited by the differential pair, and hence, more voltage swing is allowed without a significant offset of common-mode voltage.</span></span></div><div style="text-align: justify;"><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The disadvantage of the resistor-averaged CMFB is the requirement of large-valued resistors. Not only do these resistors require more silicon area, but they also load down the output and cause a reduction of the gain. Moreover, they affect output impedances, which are very critical in current-mode systems since they influence the pole and zero locations.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">One important performance factor of common-mode feedback circuits is the transconductance gain (ACMFB). ACMFB is equal to the open-loop common-mode output current (IOCM) divided by the voltage difference (VERR) between the common-mode output voltage(VCM) and the common-mode input reference voltage(VRCM).</span></span></div><div style="text-align: justify;"><br style="font-family: Verdana,sans-serif;" /></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjMfcrSUTZngA6TNMiqB0FmlsxwTEBHJubHb5A8lOKnI568l-0DF12JHFZJVKU6icSg5UO3MjCCFb_8_pquhC3FdsCqU95RXLdWRmk_mAHQC51ucYBQFdDacSWuMUENVOcdJvHAcBHH2kg/s1600/1.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjMfcrSUTZngA6TNMiqB0FmlsxwTEBHJubHb5A8lOKnI568l-0DF12JHFZJVKU6icSg5UO3MjCCFb_8_pquhC3FdsCqU95RXLdWRmk_mAHQC51ucYBQFdDacSWuMUENVOcdJvHAcBHH2kg/s320/1.bmp" /></a></div><div style="text-align: justify;"><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">With a large ACMFB, a smaller common-mode error voltage (VERR) and a faster response can be achieved. For most of the continuous-time CMFB circuits, single-stage structures are used [3][4][5][7]. For single stage DDA CMFBs[3][4][5], if the nonlinear effect of the differential can be ignored, the CMFB circuits can be simplified as shown in Figure 1. For single-stage resistor averaged CMFBs[7], the CMFB circuits can be simplified as shown in Figure 2. The differential output current is then mirrored to the output as the common-mode output current.<br />
</span></span></div><div style="text-align: justify;"><br style="font-family: Verdana,sans-serif;" /></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiPw-4lHkTFsaAqu-FMRZMhIPEel1cQg0OuRBZ9GNh6bP_pBwfygz6rhOUmA64l90LJVV0t79Sy-FZANCtzpsWKBJhS6xyt3b0PeLx8P0dAcPYkk_3Wp3OWHCpaNLrggMvH-xE80hsOd1U/s1600/2.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="223" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiPw-4lHkTFsaAqu-FMRZMhIPEel1cQg0OuRBZ9GNh6bP_pBwfygz6rhOUmA64l90LJVV0t79Sy-FZANCtzpsWKBJhS6xyt3b0PeLx8P0dAcPYkk_3Wp3OWHCpaNLrggMvH-xE80hsOd1U/s400/2.bmp" width="400" /></a></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjnd7U7b14t3gehHAF4HXUbbFZeVzJ4dIqU1SEPEc0TPfNUtHNVzmf-iZ3dYrQBLEu3U1WqpToiBcwWmMNmugxGh11qmBsu9epOeVy7O1xlhCFP3TU11baYMRnthHePVlnYVVp-TQQmpFE/s1600/3.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="217" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjnd7U7b14t3gehHAF4HXUbbFZeVzJ4dIqU1SEPEc0TPfNUtHNVzmf-iZ3dYrQBLEu3U1WqpToiBcwWmMNmugxGh11qmBsu9epOeVy7O1xlhCFP3TU11baYMRnthHePVlnYVVp-TQQmpFE/s400/3.bmp" width="400" /></a></div><div style="text-align: justify;"><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"></span></span></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">From Figure 1 and Figure 2, we find the transconductance of a single-stage CMFB is roughly equal to the transconductance gain of a differential pair. The typical transconductance gain for a differential pair is in the range of 10_A/V to 100_A/V. A 1_A common-mode offset current applied on the output causes a 10mV to 100mV common-mode error voltage (VERR). Some systems may not tolerate this amount of common-mode voltage offset. One solution to improve the transconductance gain is to use a two-stage architecture [6][8]. With one extra stage, the gain increases about 100 times, which greatly reduces the common-mode error voltage (VERR). However, the two-stage structure has a stability problem and must be compensated. Two nodes contribute to the stability problem. One is the external output node (two nodes in fact). The other is an internal node which connects the first stage to the second stage.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">For voltage-mode CMFBs with low output impedance [8], the pole caused by the external node is located in a higher frequency range. This makes the compensation easier by simply moving the pole generated by the internal node to a low-frequency location. For current-mode systems, the external nodes may have high impedance and induce a pole at very low frequencies, which is difficult to compensate. In this paper, a two-stage CMFB circuit for high impedance current-mode circuits is presented. The frequency compensation is achieved by introducing an extra pole and zero. The linearity of the DDA is improved to minimize the common-mode error voltage (VERR).</span></span><br />
<br />
<b style="color: #93c47d;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">2. Circuit Design</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The proposed continuous-time CMFB circuit is a two stage DDA CMFB as shown in Figure 3. The first stage is composed of M1 – M7 and current sources M14 – M17. The second stage is composed of M8 –M11. Long channel (small aspect ratio) NMOS transistors are used for the DDA input stage (M1 – M4) to minimize the differential pair nonlinearity and to accommodate more input voltage swing. They also minimize the VERR caused by the transistor mismatch among M1 –M4. The transistor sizes are listed in Table 1.<br />
<br />
</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEge16oEcTQEpxDYuDEz8kdD3BI2I-hGZ1hBH6cj6Fhi-08ze506657GGj-I1loPj1LMJbU3HZI264SG81AFUelyJsRQNC74wckaEvN8FAPN4wzbztbMsDSb8idZi9vQI-HmIBgTNZZ2jiQ/s1600/4.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="318" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEge16oEcTQEpxDYuDEz8kdD3BI2I-hGZ1hBH6cj6Fhi-08ze506657GGj-I1loPj1LMJbU3HZI264SG81AFUelyJsRQNC74wckaEvN8FAPN4wzbztbMsDSb8idZi9vQI-HmIBgTNZZ2jiQ/s400/4.bmp" width="400" /></a><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsWGPKpY7siguTyEJdhoJOdFNwT3iY5YtKn_XNnlG7ZBnNf-ZTtnmymLWoDveBKtc-jxcc0BPmcfWbyXM3lINT6oRwEIl8VoS9bWMTKuht27T3cJe0vphgnrlekz8YdocBx3Ltok79Lzc/s1600/5.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="220" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsWGPKpY7siguTyEJdhoJOdFNwT3iY5YtKn_XNnlG7ZBnNf-ZTtnmymLWoDveBKtc-jxcc0BPmcfWbyXM3lINT6oRwEIl8VoS9bWMTKuht27T3cJe0vphgnrlekz8YdocBx3Ltok79Lzc/s400/5.bmp" width="400" /></a></div><div style="text-align: justify;"><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"></span></span></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Two high-impedance places, two external nodes (A) and one internal node (B) in Figure 3, introduce two low frequency poles and cause a stability problem. Frequency compensation is achieved by adding MC and CC. With CC shunted to the input and output of the first stage, an extra pole and zero are introduced to attenuate the high frequency gain of the first stage. The gain of the first stage reduces to one for a high-frequency range and causes the CMFB to function as a single-stage CMFB. Accordingly, the proposed CMFB has a large low-frequency gain to minimize VERR and a moderate high-frequency gain to keep the system stable.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 4 shows the compensation scheme of the proposed <a href="http://cmfb.mc/">CMFB.MC</a> and CC (in Figure 3) introduce an extra low-frequency zero to correct the phase shift and an extra high-frequency pole, which has an insignificant effect on the performance. In the proposed CMFB, the common-mode error voltage (VERR) is caused mainly by the transistor mismatch, which is in the mV range.<br />
<br />
</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjZOMvS_d6SgKocf6MOfyTLMqvYsk2cp7M9b9gRHCaNPPX6SvEqcA6Q2bLuJeOKgKQkZDtT81WbY4IGlV_W0eJwLSnfafZ_hR6U6YAO8kNH43ntjAbDiFCVTOkl9E9pJA5fqImwVF_ccjw/s1600/6.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="281" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjZOMvS_d6SgKocf6MOfyTLMqvYsk2cp7M9b9gRHCaNPPX6SvEqcA6Q2bLuJeOKgKQkZDtT81WbY4IGlV_W0eJwLSnfafZ_hR6U6YAO8kNH43ntjAbDiFCVTOkl9E9pJA5fqImwVF_ccjw/s400/6.bmp" width="400" /></a></div><div style="text-align: justify;"><br />
<b style="color: #93c47d;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">3. Experiment Result</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The proposed CMFB has been implemented in a second order continuous-time switched current Σ∆ modulator (Fig. 5) in a 2um CMOS process [9]. The accuracy and stability of the common-mode voltages in the Σ∆ modulator are important since they affect the gain of the Voltage-to-Current Converter (in Figure 5) due to the body effect [9].<br />
<br />
</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj8zplyY2S13v_YDkSbxA4JXOUX8CUz6w8QrcN7g8f4NjBNCfMq1GGGYRRX97Vk0ztHVGjFj1U4gw4PW07RDS3RD6HbxD24UCXS8pjEk-tnT0ZBihatEX51ac8PxnjWXGC_Bwb9lbouyBo/s1600/7.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="262" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj8zplyY2S13v_YDkSbxA4JXOUX8CUz6w8QrcN7g8f4NjBNCfMq1GGGYRRX97Vk0ztHVGjFj1U4gw4PW07RDS3RD6HbxD24UCXS8pjEk-tnT0ZBihatEX51ac8PxnjWXGC_Bwb9lbouyBo/s400/7.bmp" width="400" /></a></div><div style="text-align: justify;"><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The proposed CMFB is designed to accommodate ± 1V differential voltage swing. Figure 6 shows the relationship between VERR and the differential input voltage within±1V. From Figure 6, VERR is less than 0.4mV within the designated differential input voltage range. Here, the mismatch among M1–M4 is ignored. Figure 7 shows an expanded view of VERR over the differential input range within ± 2V.<br />
<br />
</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg7J83bA7d9-ZbR_AHQp8FUQp-BxftKtWOYx8niJbcpRp74OGH_ONmR4YDHlUn9ZhmuEI3dfs0NeTbLUzGFIhkxouJgWk9jOOHVIPjTPk8j9fIYyx3TiMPSYZvoyapfy2RDXHwIQ-XCMvE/s1600/8.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="326" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg7J83bA7d9-ZbR_AHQp8FUQp-BxftKtWOYx8niJbcpRp74OGH_ONmR4YDHlUn9ZhmuEI3dfs0NeTbLUzGFIhkxouJgWk9jOOHVIPjTPk8j9fIYyx3TiMPSYZvoyapfy2RDXHwIQ-XCMvE/s400/8.bmp" width="400" /></a></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjau0GZ6jJuJI1KF1e8-ptLjimvPa6dM7VUJkibd_HmpuTdRxVP5QGjTMlOZxCAIr9_ADxxN3KfNNrSN7TQ4JbSvq4VZvqqVMzo9Q18dWBcWMZOeWkn_AEFxcE0F-m4TNgn15g-2QorHC4/s1600/9.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="297" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjau0GZ6jJuJI1KF1e8-ptLjimvPa6dM7VUJkibd_HmpuTdRxVP5QGjTMlOZxCAIr9_ADxxN3KfNNrSN7TQ4JbSvq4VZvqqVMzo9Q18dWBcWMZOeWkn_AEFxcE0F-m4TNgn15g-2QorHC4/s400/9.bmp" width="400" /></a></div><div style="text-align: justify;"><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 8 shows the open-loop transconductance of the proposed CMFB. The performance summary is shown in Table 2. Figure 9 shows a microphotograph of the proposed CMFB circuit. A second-order continuous-time switched-current Σ∆ modulator with the proposed CMFB has been implemented in a 2u CMOS process and achieved 60dB dynamic range with a 50MHz clock.<br />
<br />
</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjbnA0EXjcAA7RY6JOwZBxEZ6j3VHhoCTWqpQP3Oddip8kyTOAHPiRakmRFYIiQ3oCcsHW1OV5UyWr6OIzyQljw7EGr7RwRZzqsRlawTVzUNLOEWAemMNKLV3MVC-kEAmF8T9_OrK53JWo/s1600/10.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="326" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjbnA0EXjcAA7RY6JOwZBxEZ6j3VHhoCTWqpQP3Oddip8kyTOAHPiRakmRFYIiQ3oCcsHW1OV5UyWr6OIzyQljw7EGr7RwRZzqsRlawTVzUNLOEWAemMNKLV3MVC-kEAmF8T9_OrK53JWo/s400/10.bmp" width="400" /></a></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhw-kXh6i33RrRCta1mx9cOW4jCE1jzQ901t5Sc1AYMzxhKK2gElXjimffLY8ritKWE31ORx34rGTJeDLz28U2DRLa90pmT5YLMv1tRx68VByxvGMjmZtun6tV0ptYb-F_GVfgfnOs0AfQ/s1600/11.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhw-kXh6i33RrRCta1mx9cOW4jCE1jzQ901t5Sc1AYMzxhKK2gElXjimffLY8ritKWE31ORx34rGTJeDLz28U2DRLa90pmT5YLMv1tRx68VByxvGMjmZtun6tV0ptYb-F_GVfgfnOs0AfQ/s400/11.bmp" width="400" /></a></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhzXbi5cx6lJFH0uXyJtna250_atRYaYq0HXV4NmykLIzPcKGQGUNGIOX-BQEDpa8lSnhgKBfIm7NbygbhVIK_QrN-O1u1V07H5Xx8Rwr9YWj93CMiOeXdTWtD4B6sqPAqM1qv1UQ1wFak/s1600/12.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="347" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhzXbi5cx6lJFH0uXyJtna250_atRYaYq0HXV4NmykLIzPcKGQGUNGIOX-BQEDpa8lSnhgKBfIm7NbygbhVIK_QrN-O1u1V07H5Xx8Rwr9YWj93CMiOeXdTWtD4B6sqPAqM1qv1UQ1wFak/s400/12.bmp" width="400" /></a></div><div style="text-align: justify;"><b style="color: #93c47d;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">4. Conclusion</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">A continuous-time common-mode feedback circuit is presented. The two-stage CMFB structure minimizes the common-mode error voltage without a stability problem. The high output impedance and small common-mode error voltage make it an ideal CMFB, even for a high impedance current-mode system. The proposed CMFB can be easily implemented in any differential mode circuits without modifying differential amplifiers or other circuits in the system. The measured result of the second order continuous-time switched-current Σ∆ modulator has proven the superior performance of the proposed CMFB.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Hernández Caballero Indiana</span></span><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Asignatura: CAF</span></span><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Fuente:<a href="http://citeseerx.istpsu.edu/">http://citeseerx.istpsu.edu</a></span></span></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-31487625254141895122010-07-25T23:32:00.002-04:302010-07-27T16:51:38.264-04:30High Performance Fully Differential Opamp for a Pipeline ADC Stage<div class="post-header"></div><div style="text-align: justify;"><br />
<span style="font-family: Verdana, sans-serif; font-size: small;"><b style="color: #93c47d;">Abstract</b>—This report presents a fully differential operational amplifier (opamp) for a pipeline analog-to-digital (ADC) with high gain (110 dB), ample phase margin (67.8°), low input capacitance ( 1.5 pf) and fast settling time (29.03ns) designed in a 2.5 V, 0.250 um CMOS process. The opamp consumes 59.2mW of power and 800um x 400um of area. The opamp's performance was verified over 0-100 C and three process corners. </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Index Terms—common mode feedback, gain enhancement, opamp, pipeline ADC </span></div><div style="text-align: justify;"><br />
<b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;">I. INTRODUCTION </span></b><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">HIS report presents a fully differential opamp designed for a pipeline ADC stage. Table 1 highlights the specifications for the design. The implementation of this design must have high gain and a fast settling time. The quickness of opamp settling determines the speed of the pipeline ADC, thus fast settling is desirable. The higher the gain of an omamp the more ideal it is, and in feedback gain approaches 1/β with less error. [1] presents a design with high gain and high unity gain bandwidth though their implementation was in a significantly different process than ours. The authors present a differential folded cascode amplifier with gain enhancement, as well as presenting relevant background on gain enhancement. The authors were able to achieve a gain in excess of 90 dB, which exceed the specification for our project. We therefore chose the enhanced folded cascode architecture as the basis of our design </span></div><div style="text-align: justify;"><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">The folded cascode provides the needed headroom for an output swing in excesss of 1Vpk. With enhancement a high gain is possible, as [1] showed. </span><br />
<br />
<b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;">III. CIRCUIT DESCRIPTION </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">A. Architecture </span></b><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Figure 1 highlights the architecture of the opamp that was designed. A fully differential in and out amplifier was </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">realized. A folded cascode differential amplifier was chosen in order to support the specified output swing of 2 volts peak to peak.. The folded cascode design was also selected for its high output impedance. Bias current is mirrored with PMOS devices across the top of the schematic. Gain enhancement boost amps were designed and implemented to increase the output impedance of the folded cascode and meet specified gain. PMOS inputs were selected to minimize the capacitance at the drain node of the input devices, as NMOS are more area efficient, to improve phase margin. Bias voltages are generated in the block I33 using ratios of NMOS and PMOS sizing. Finally, common mode feedback was implemented in order to improve output swing. </span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjb41GO0-r5UsV5fWLvzzwV0wCHTulCZFRbL2EFCYZ4fwsGMlan1n6pifsnNCOfQ7V8xY1i4AKJyjbwVWvHy8ChIRY4GqDxAamdDiXA_if2Rg6ogUB4lbH2FzESNNICXqQEBGB8dRbqqp8/s1600/1.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="255" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjb41GO0-r5UsV5fWLvzzwV0wCHTulCZFRbL2EFCYZ4fwsGMlan1n6pifsnNCOfQ7V8xY1i4AKJyjbwVWvHy8ChIRY4GqDxAamdDiXA_if2Rg6ogUB4lbH2FzESNNICXqQEBGB8dRbqqp8/s400/1.bmp" width="400" /></a></div><div style="text-align: justify;"><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;"> </span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">B. Gain Enhancement </span></b><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Figure 2 highlights the architecture of the gain enhancement that was implemented. A differential in single ended out opamp with gain A works to resist changes in the gate source voltage of M2 increasing the effective output resistance of the cascode of the by A. The gain enhancement also adds robustness to temperature and process variation. The gain boost opamp positive terminal takes a reference voltage that can be selected to ensure the drain source voltage of M1 remains large enough to ensure M1 stays in the saturation region which gives the highest output impedance. </span><br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgMdefO6HQv-ACbtCGN2CQ3EH9ioInZtyvlfwUK2n2N-GNn5omDCUojunWRy0Bi1FxDzoiXSFaKNn7iCSp6Jp4AMSmh1tsy1Gp02OBnqP2hThH1JrFjph1mg8VL2Wa4PTQTDSYr2aYvAn8/s1600/2.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="197" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgMdefO6HQv-ACbtCGN2CQ3EH9ioInZtyvlfwUK2n2N-GNn5omDCUojunWRy0Bi1FxDzoiXSFaKNn7iCSp6Jp4AMSmh1tsy1Gp02OBnqP2hThH1JrFjph1mg8VL2Wa4PTQTDSYr2aYvAn8/s400/2.bmp" width="400" /></a></div><br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiq4Q0oR9XWpeDcAP3u8k8VdMa6XWfHiMRJ25ZM-bdmCgaOzdxkWkn8EzXwCkMB_vDpV6E1QjmbiuV4CbQ4KRICbe6sG3iMX9yL4R3EvHpMm1eTL1dQx565-9E_LQwNJjyudxVQ61IjMPw/s1600/3.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="141" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiq4Q0oR9XWpeDcAP3u8k8VdMa6XWfHiMRJ25ZM-bdmCgaOzdxkWkn8EzXwCkMB_vDpV6E1QjmbiuV4CbQ4KRICbe6sG3iMX9yL4R3EvHpMm1eTL1dQx565-9E_LQwNJjyudxVQ61IjMPw/s400/3.bmp" width="400" /></a></div><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">The gain boost amplifiers were implemented with single ended output folded cascode opamps as shown in [4]. </span><br />
<br />
<b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;">D. Common Mode Feedback </span></b><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Common mode feedback is necessary to regulate the common mode of the differential outputs of the opamp to ensure a large output swing. In figure 1 the common mode feedback circuit block is within the center of the two halves of the folded cascode. A simplified schematic of the common mode feedback circuit can be seen in figure 3. The current sources in the figure represent the pmos current mirrors. Vout+ and Vout- are the outputs of the enhanced folded cascode. Vset is a reference voltage that needs to be insensitive to temperature and process variations, to ensure constant common mode output. Vset is generated using two equally sized NMOS as a voltage divider to set VSET ideally to half of VDD. The diode connected NMOS is used to mirror current back into the folded cascode stack. </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">The circuit operates as follows: as the output common mode rises more of the current from the current sources is sunk through the outside legs of the circuit, and thus through the diode connected NMOS current mirror at the bottom of the circuit. This increase in current through the NMOS causes an increase in current within the folded cascode stack, forcing the output common mode to fall. Thus a form of negative feedback exists that regulates the output common mode. </span></div><div style="text-align: justify;"><br />
<span style="color: #93c47d; font-family: Verdana, sans-serif; font-size: small;"><b>IV. CIRCUIT ANALYSIS</b> </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">The most challenging target specification was the 12bit settling time of 4ns. According to equation (1) and (2) a unity gain frequency of 1.3GHz is necessary to meet this specification.</span><br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhhnnUplgSFHAb6Iz5T30OWj-nkYgNmClPi04zwSvrlNhVqakzVHN-Zx7CfyJQSUC9oXvhB31QqJausmi54x4LLRNOdp-E8AwBYMtQHOPZPi8nwkERwoYYipkiNLrQM21HzV6IBOBdZJps/s1600/4.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhhnnUplgSFHAb6Iz5T30OWj-nkYgNmClPi04zwSvrlNhVqakzVHN-Zx7CfyJQSUC9oXvhB31QqJausmi54x4LLRNOdp-E8AwBYMtQHOPZPi8nwkERwoYYipkiNLrQM21HzV6IBOBdZJps/s320/4.bmp" /></a></div><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Using our output capacitance specification of 5pF in equation (3) the required gm of the input PMOS was calculated to be 6.5mS.</span><br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiAnFh5XOu0cFQprJunzIj4NIIfjl8VywroFbXFkL7kcuiPz4RcXmhMiDDpAZQHskIQKVevVqDJFe1Rc4-jmeyQ7MB8i56-C5PK615HdLPdAd9R98FLQy_pT0lp09Kt7vpqL-99cwymQoU/s1600/5.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiAnFh5XOu0cFQprJunzIj4NIIfjl8VywroFbXFkL7kcuiPz4RcXmhMiDDpAZQHskIQKVevVqDJFe1Rc4-jmeyQ7MB8i56-C5PK615HdLPdAd9R98FLQy_pT0lp09Kt7vpqL-99cwymQoU/s320/5.bmp" /></a></div><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Using the gm of 6.5mS, we solved for the output impedance necessary in a non-boosted folded cascode to obtain a gain of 84dB. Drain current values through the drivers and the cascode devices were found using simplified hand calculation expressions for gm and rO and assuming all devices would operate in saturation. Device were initially sized using the MOSFET current equation and the drain current values that we calculated. </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">When this design was initially implemented, all devices operated in the correct region but gain, at approximately 40dB, was much lower than required. Common mode output voltage was also around 2V for each half circuit which would not allow the circuit to swing over the output range we desired. To overcome these shortcomings gain boost amplification and common mode feedback was added to the circuit. Design of the boost amps was based off of the sizings already generated for the fully differential circuit, but with current mirroring between half circuits to make the design differential in / single ended out. Design of the common mode feedback was based on of the NMOS folded cascode CMFB used in [2]. </span></div><div style="text-align: justify;"><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Implementation of CMFB and gain boosting gave us a circuit with an output DC voltage of around 1.25V which allowed the output to swing farther than required. It also resulted in a surplus of gain, producing around 120dB. Our unity gain frequency started out at around 250-300MHz in our intial design when driving the 5pF load cap. Increasing gm of the input transistor was used initially to raise this value, but when used alone the sizing of this device became impractical and capacitive loading of internal nodes by this device became pronounced. To push out ωunity we systematically scaled down the lengths and overall W/L ratios of devices connected to the output node and the intermediate cascode node. This allowed us to achieve a nominal ωunity of around 850MHz into the 5pF load with good single pole behavior throughout the amplifiers frequency response. An optimal input driver size was found such that scaling the driver down hurts performance and scaling the driver up yields no significant gains and a large area and power consumption cost. </span></div><div style="text-align: justify;"><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">To achieve stability and an acceptable phase margin the unity gain frequency of our boost amps needed to be slowed from their initial state. This was accomplished by attaching a capacitive load of 4.5pF to the output of each boost amp. This did not negatively affect overall ωunity and gave us a good 60-70 degree worst case stability (β = 1) phase margin for the overall circuit. </span></div><div style="text-align: justify;"><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Our final design was very robust overs changes in bias voltage so biases were set with simple resistive divider circuits using diode connected PMOS and NMOS devices. The most important bias voltage for op-amp operation was Vset, the input voltage to the common mode feedback. This voltage was set using a divider of two identical diode connected NMOS devices so it does not depend on an N to P ratio to set its value. </span><br />
<br />
<b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;">V. RESULTS </span></b><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">The fully differential opamp was designed in Cadence and simulated over slow, nominal, and fast process corners and at 0°, 27°, and 100° C. Layout of the device was also completed, and all presented results include extracted parasitics. Figure 4 below shows the open loop magnitude and phase plot. A fully differential frequency dependant input was swept to determine gain, unity gain freq, 3 dB bandwidth, and phase margin. Phase margin was measured for unity gain feedback to measure worst case stability. Simulated gain exceeded the target of 84 dB, with a value of 110 dB at 27 C. Unity gain bandwidth was 885 MHz which is less than 1.3 GHz target for a theoretical 12 bit settling time of 4 ns, for nominal process and 27 C. </span></div><div style="text-align: justify;"><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Transient analysis was also completed to measure output swing, and settling time. Transient analysis was completed with inverting feedback with a feedback factor of ¼, as shown in figure 5. Ideal feedback was implemented by using a voltage controlled voltage source with unity gain to decouple the output of the opamp from the feedback network. A resistive divider network of 1kΩ and 3kΩ, giving a beta of ¼ and an ideal gain of 3. Figure 6 shows a transient response focusing on the rising edge of the output for a differential switch in the input. There is not ringing in the output as expected for a unity gain feedback phase margin of 67°. Phase margin > 60° was achieved for all process corners and temperatures. This the opamp has sufficient phase margin to ensure stability. The feedback factor of ¼ also adds to this stability. (Add schematic) Settling time was measured over all process corners and 0,27, and 100 °C. The 12 bit settling time for the average case (27 °C, nominal process) was measured with the settling time calculator in Cadence to be 29.03 ns. The best 12 bit settling time measured was 17.99 ns (0 °C, nominal process). The worst 12 bit settling time measured was 91.65 ns (0 °C, slow process). All measured settling times were greater than the target of 4 ns for this project. </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">The output swing specification of 1 Vpk was met over all process corners and temperatures. Output swing was verified by checking to ensure that the opamp was not railing out and that an output swing greater than 1 Vpk could be achieved. Figure 7 shows an output swing greater than 1 Vpk (27 °C, nominal process). Stability of the opamp at this operating point is also evident. Table II highlights the 10 bit settling time, unity gain bandwidth, gain, and phase margin over all temperature and process corners considered. Target settling time of 4 ns for 12 bits was specified, but 10 bit settling time was also measured with cursors in Cadence. Data is reported to show variance with process and temperature. </span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Table III provides a performance summary of the opamp for the average case (27 °C, nominal process). </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Figure 8 shows the device layout. It closely follows the schematic and fits in an area of 800umx400um. Routing is restricted to metals 1 through 3 avoids routing over devices. The layout is DRC and LVC clean. </span><br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi1WWRqUriifJ9T-GiPCH-_IDg3ILuQTgyWZiCAhLDOjY6EPCr1UxLuTMrU7cIHrCb4B9r57K2cMbm5FN8F6OZyCXg2BAcv5ffnhXtUpeOZAvenGHEFrysOJWv33ejFKAGXBIWOwcZVF4g/s1600/6.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="177" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi1WWRqUriifJ9T-GiPCH-_IDg3ILuQTgyWZiCAhLDOjY6EPCr1UxLuTMrU7cIHrCb4B9r57K2cMbm5FN8F6OZyCXg2BAcv5ffnhXtUpeOZAvenGHEFrysOJWv33ejFKAGXBIWOwcZVF4g/s400/6.bmp" width="400" /></a></div><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh4YusGFdUJi-vlRc_syYF7du8i3WXHBBk1b6ZKYVOa8TbS1NuI7LNSR2Zutv1YaXRrWfLMdbTnMoluKdoVdJMxk3JZ6SsjG9Uj-O-3U2Aix1iGewLMSXPVarevTctIBw3WipA7jajL-zQ/s1600/7.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="270" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh4YusGFdUJi-vlRc_syYF7du8i3WXHBBk1b6ZKYVOa8TbS1NuI7LNSR2Zutv1YaXRrWfLMdbTnMoluKdoVdJMxk3JZ6SsjG9Uj-O-3U2Aix1iGewLMSXPVarevTctIBw3WipA7jajL-zQ/s400/7.bmp" width="400" /></a></div><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiBXUjvkKvtz2sigjjTj7IiOIGFGQgkcBKstrZjPKEroGX7GJ1TObneo_fBLiZesdE-LbBKxEYGbACnWCOxLgTlMmwAjSz9VjPQWf5CEiybWJ2P75BBfHLPWsj66bRyOczWEV-PB8PdjGs/s1600/12.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiBXUjvkKvtz2sigjjTj7IiOIGFGQgkcBKstrZjPKEroGX7GJ1TObneo_fBLiZesdE-LbBKxEYGbACnWCOxLgTlMmwAjSz9VjPQWf5CEiybWJ2P75BBfHLPWsj66bRyOczWEV-PB8PdjGs/s320/12.bmp" /></a></div><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhy8Brb-VEeJPccCD3GIB5nL3aOzNEcmVUbI3g72hViVF4vhCsVXpkz6Z5_VrSJEv0W_57KMuxzx7Aio42HOBIsO1XvlBqESXHgknR8OXfCKdC8ZdUweVRZc_Xrulg8Dk32solo7VULdKs/s1600/8.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhy8Brb-VEeJPccCD3GIB5nL3aOzNEcmVUbI3g72hViVF4vhCsVXpkz6Z5_VrSJEv0W_57KMuxzx7Aio42HOBIsO1XvlBqESXHgknR8OXfCKdC8ZdUweVRZc_Xrulg8Dk32solo7VULdKs/s320/8.bmp" /></a></div><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEilZ-zv2kCB3JvMrtMK5JbY7Relr0DB7yAbWMb1cZXPpqiVfgguLzVEdRx3L4TK5LlU4Ft4q-Qh0WZaPOOf2n9HYqAzotju89bxpy4eh6ydEf3owqWaD-b3BXQ7pdzCb2BqkYMnu5z_KrI/s1600/9.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEilZ-zv2kCB3JvMrtMK5JbY7Relr0DB7yAbWMb1cZXPpqiVfgguLzVEdRx3L4TK5LlU4Ft4q-Qh0WZaPOOf2n9HYqAzotju89bxpy4eh6ydEf3owqWaD-b3BXQ7pdzCb2BqkYMnu5z_KrI/s320/9.bmp" /></a><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgnOwohyphenhyphenF1yJDfkZJTBhoBOR_Sv3ObAg4e9siQpURrzS6QsIYJoAq631EOYdvxxGHt6wiKBKC3vkWh6QaUTKZau3UpXq7-8TopoRvGShB5v9V6bB4QsDL1jeyVkbrEGYFdT3_59KxH4qA8/s1600/10.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgnOwohyphenhyphenF1yJDfkZJTBhoBOR_Sv3ObAg4e9siQpURrzS6QsIYJoAq631EOYdvxxGHt6wiKBKC3vkWh6QaUTKZau3UpXq7-8TopoRvGShB5v9V6bB4QsDL1jeyVkbrEGYFdT3_59KxH4qA8/s320/10.bmp" /></a></div><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg3Czz0xliAVUqUpfsGgkV6pUCQkNfY79kx2hhfasmb8r7TTj-bEEeGiQi5IOmMh7OMraaOFQhdh_5cBB3TGPqSRy8fojq3RwMAMqemZzj9mXuzx831XoiUrf5YpKe26Tb0zya8tvVGalg/s1600/11.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg3Czz0xliAVUqUpfsGgkV6pUCQkNfY79kx2hhfasmb8r7TTj-bEEeGiQi5IOmMh7OMraaOFQhdh_5cBB3TGPqSRy8fojq3RwMAMqemZzj9mXuzx831XoiUrf5YpKe26Tb0zya8tvVGalg/s320/11.bmp" /></a></div><br />
<b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;">VI. CONCLUSION </span></b><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">A fully differential opamp for a pipeline ADC was realized with an enhanced folded cascode opamp with high gain (110 dB), ample phase margin (67.8°), low input capacitance ( 1.5 pf) and fast settling time (29.03ns) for nominal process corner, 27° C The opamp consumes 59.2mW of power and 800um x 400um of area. </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">The design met specs for output swing(>1 Vpk), input capacitance (<4pf), and phase margin(>60°) for all process corners and temperatures. Thus design was sufficient output swing and stability all tested operating conditions. The design exceeded the spec for gain (> 84 dB) for all process corners except for the case of slow process and 100°C. Thus gain is very stable over many operating conditions. </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">The design was unable to meet the target 12 bit settling time of 4 ns over any process corners and temperatures. This is where the design could be improved. This design would have better settling behavior or a smaller load cap. If there was room for greater input apacitance ore transconductance could have been realized increasing the unity gain requency and potentially further reducing the settling time.</span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Hernández Caballero Indiana</span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Asignatura: CAF</span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Fuente:<a href="http://www.eecs.umich.edu/~mpflynn/teaching/design_contest/fall_2005/reports/group4_eecs413_F05.pdf">http://www.eecs.umich.edu/~mpflynn/teaching/design_contest/fall_2005/reports/group4_eecs413_F05.pdf</a></span></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-11195556456310717802010-07-25T23:31:00.002-04:302010-07-27T16:51:19.724-04:30COMMON MODE STABILITY IN FULLY DIFFERENTIAL VOLTAGE FEEDBACK CMOS AMPLIFIERS<h3 class="post-title entry-title"><a href="http://indianamaithe.blogspot.com/2010/07/common-mode-stability-in-fully.html"></a> </h3><div class="post-header"></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><b style="color: #93c47d;">ABSTRACT</b><br />
<br />
In this study consideration is made of the common mode (CM) behavior of two-stage fully differential amplifiers in voltage feedback connection. In particular, interaction between internal CMFB circuitry and the external feedback network is investigated in order to highlight a possible operating point instability condition, due to the presence of a positive feedback loop. Two alternative CMFB topologies are compared, one of which is affected by instability, with development of constraints on the feedback network parameters to be fulfilled in order to avoid instability. Comparison was made by circuit simulations with reference to a low voltage, deep sub-micron CMOS technology (0.12 μm) implementation of a differential amplifier.<br />
<b style="color: #93c47d;"><br />
1. INTRODUCTION</b></span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
Fully differential circuit structures are at present widely employed in low voltage (LV) applications, due to their improved immunity to noise, larger output swings and reduced distortion. However, these benefits are obtained at the expense of greater complexity, since differential amplifiers usually require internal common mode feedback (CMFB) loop in order to stabilize their d.c. voltages at both internal and output nodes. Although a great amount of work is currently underway which addresses this problem either by optimizing the CMFB loop in terms of linearity, speed, power consumption, and so on [1,2], or by trying to control the CM without employing any additional circuitry [3,4], no general solution is presently available since the variety of different situations arising in practical applications requires special approaches. This study shows that two distinct CMFB loops are generally active in a differential voltage amplifier with internal CMFB circuitry [5] and identify the conditions for which their interaction point at the amplifier power on. Fig.1 shows the schematic of a differential voltage amplifier implemented with a fully differential Opamp. One of the feedback loops, internal to the Opamp, includes the CMFB circuitry, while the other is made up of the external passive feedback network and the CM signal path of the Opamp. While the former achieves negative feedback, the latter is positive for a typical two-stage amplifier, and may cause instability.</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhJwaFlVYGbk0-h0tQLR1fn0ajMDKaa_f6NnROmcNwcEVtX-6zacPbLFgCZo5tj2aZ9FFv-I0eZ4Qb0evm9a1Y0m8f0G3IaXqxQvjVKE2_MmEXpEzSFPxckhWbyeSn23nn4aZkaqv9p7sg/s1600/1.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="166" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhJwaFlVYGbk0-h0tQLR1fn0ajMDKaa_f6NnROmcNwcEVtX-6zacPbLFgCZo5tj2aZ9FFv-I0eZ4Qb0evm9a1Y0m8f0G3IaXqxQvjVKE2_MmEXpEzSFPxckhWbyeSn23nn4aZkaqv9p7sg/s400/1.bmp" width="400" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
In order to distinguish between the two loops, the former is referred to as 'internal', while the latter is 'external'. According to this definition, Tint and Tex represent corresponding loop gains while V'icm, Vicm and Vocm are CM voltages at nodes 1-2, 3-4 and 5-6 respectively, as indicated in Fig.1.<br />
<b style="color: #93c47d;"><br />
2. ANALYZING THE CMFB LOOP</b><br />
<br />
The problem can be studied in its essential aspects with reference to simple Miller Opamp architecture, although analysis can easily be extended to more complex situations including both telescopic and folded cascode topologies, circuits or opamps. An initial CMFB topology is analyzed here which sets up CM control by regulating gate voltage across M0, as shown in Fig.2. In this figure, ACMFB, which is negative, represents the voltage gain of the CMFB circuit, while M0 is in the saturation region. Apparently, the amplifier has a non-inverting common-mode gain, Acm, resulting as it does from cascade connection of two inverting stages. As a consequence, as has already been pointed out, a positive feedback effect arises when the external differential feedback network is connected which may affect overall amplifier stability. In fact, denoting the feedback factor by:</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh1PxHEcqOMktGIkNnrdSnclQ91h9vehkViP83VmNOi_XiaEeRKLrV4AbEwqvBWnHWInbAEL8mF6Ah6eTHkOrVMkHD7_agg7B7tKE3O1blM5cRee9OwBURQ9uTvF-mFZwK6-zUwNVuIMe8/s1600/f.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh1PxHEcqOMktGIkNnrdSnclQ91h9vehkViP83VmNOi_XiaEeRKLrV4AbEwqvBWnHWInbAEL8mF6Ah6eTHkOrVMkHD7_agg7B7tKE3O1blM5cRee9OwBURQ9uTvF-mFZwK6-zUwNVuIMe8/s320/f.bmp" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
The external CM loop gain, Tex = Acm.f, must be kept smaller than unity so as to avoid instability.</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi7UMJdbI7jZ1aC1wz8pj_IY3qyG79Gcipl3mEiK1wSgzjyESKxCdb3vStvHlZ1Jq0DxJRT64SEYY7-K2IJmx5aFEzp_x7T4jK67QprdUMAtAtiSTET2qxt_DRMBiorhRop_sizFR6VIFw/s1600/2.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="280" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi7UMJdbI7jZ1aC1wz8pj_IY3qyG79Gcipl3mEiK1wSgzjyESKxCdb3vStvHlZ1Jq0DxJRT64SEYY7-K2IJmx5aFEzp_x7T4jK67QprdUMAtAtiSTET2qxt_DRMBiorhRop_sizFR6VIFw/s320/2.bmp" width="320" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"> In particular:</span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgvqQaiHcXY1Q7QG8Wi3v00zWRjJJGrqbGjxG2EpoSmA4HF0sZ1xkaCEBNr8ERj-KMOOVDnVnIL61iOKt_9Tjf-ny2VXckMCszbSYSolZewdHE7mTF9sccMqrN3n8BLNQdJhHpw4FVhfPI/s1600/3.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgvqQaiHcXY1Q7QG8Wi3v00zWRjJJGrqbGjxG2EpoSmA4HF0sZ1xkaCEBNr8ERj-KMOOVDnVnIL61iOKt_9Tjf-ny2VXckMCszbSYSolZewdHE7mTF9sccMqrN3n8BLNQdJhHpw4FVhfPI/s320/3.bmp" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
Where: Acm0 is the CM gain without the CMFB circuit and Tint is the internal CM loop gain. Defining the impedances at the drain of the cascode and output transistors by rp1 and rp2 respectively, Tint can be calculated from the CM half circuit of the amplifier shown in Fig.3:</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjC2kl8tQhnAp6iD6fsEFTMqumF0j_wJAgIfRMLrnnxFR1nXyZs-MBG-fdOsTQuDy8xTwt5EV3fs7Ncp4cT1gAWidGuW02HGc3SssvAENsf4z3Ys0iYfRW2aOlMkLEmq0ZTZltw7L2XIOo/s1600/4.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="61" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjC2kl8tQhnAp6iD6fsEFTMqumF0j_wJAgIfRMLrnnxFR1nXyZs-MBG-fdOsTQuDy8xTwt5EV3fs7Ncp4cT1gAWidGuW02HGc3SssvAENsf4z3Ys0iYfRW2aOlMkLEmq0ZTZltw7L2XIOo/s320/4.bmp" width="320" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">As Acm0 has a low value due to the high CMRR of the Opamp, Acm will normally be very small.</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
However, with reference to the CM loop in Fig.2, an increase of the CM signal Vicm, at the input of the amplifier, may lead the transistor M0 to operate in its triode region, in which case the circuit assumes a nonlinear behavior since the M0 output resistance is no longer constant. Reducing output resistance of the tail current source will cause a decrease in CMRR and an increase in Acm0, with Tint also dropping owing to its proportionality to gm0. As a result, Acm increases along with Tex. The amplifier d.c. operating point is determined by the equilibrium condition resulting from the simultaneous action of both internal and external feedback loops. If V'icm = VREF = cost., the expression of the static characteristic of the external feedback network is simply:</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhC2WBpFawGR_rRhCnMeb5tmqgm8ZE0LbdcBoVyO57fqaymCJ5WWqGsScsy88v7D34VFtWXLSdOPYzJuX7OPqgxT0VWjqkaimYefn_8SOxy0_CJRujQXoWcf0PuXuKXJsSnEJDgv_f7tfU/s1600/5.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="301" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhC2WBpFawGR_rRhCnMeb5tmqgm8ZE0LbdcBoVyO57fqaymCJ5WWqGsScsy88v7D34VFtWXLSdOPYzJuX7OPqgxT0VWjqkaimYefn_8SOxy0_CJRujQXoWcf0PuXuKXJsSnEJDgv_f7tfU/s320/5.bmp" width="320" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhC2JSyD8KMVcBlGmoM2pIXzAmHdFdmhUiq4blRuhWnSQdiQ77-TZnEd8euRP425wrbwlcne2qQ50EJEC_qrOS9yBa_tMmk5eyzHpS8gfU_e1pLCqmtmW1LJPzrmo5r7JP24ZUKDtJOCJQ/s1600/6.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="76" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhC2JSyD8KMVcBlGmoM2pIXzAmHdFdmhUiq4blRuhWnSQdiQ77-TZnEd8euRP425wrbwlcne2qQ50EJEC_qrOS9yBa_tMmk5eyzHpS8gfU_e1pLCqmtmW1LJPzrmo5r7JP24ZUKDtJOCJQ/s400/6.bmp" width="400" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">Graphical representation of this relationship, with k= R2 / R1, is shown in Fig.4 (solid lines). The slope of these characteristics is 1/f. The dashed curve refers to the static input-output CM characteristic of the Opamp. The equilibrium condition must satisfy the constraints imposed by both characteristics and corresponds to the intersection of the two curves of Fig.4. Owing to the non-linearity of Acm, the equilibrium condition may not be univocally identified, also depending on the values assumed by the two resistors R1 and R2. In particular, a range [0, k*] exists, such that three distinct intersection points occur when 0 < k < k*, while a single equilibrium point exists for k > k*. For example, assuming VREF = 0.7 V and VDD = 1.5 V leads to a value of k* = 1.67 (obtained by setting Vocm = VDD and Vicm = VDD-VSG-VSDsat in eq. (2)). Thus even a simple, widely employed, voltage buffer (k = 1) may be affected by the described operating point ambiguity. Analysis of Fig.4 appears to indicate that for k within the interval [0, k*], points 1 and 3 correspond to stable equilibrium conditions, since they refer to low values of Acm, while point 2 is unstable, since it occurs in correspondence with a high Acm value. This is also apparent from evaluation of the slope of the dashed line at point 2. Under these conditions, in fact, Acm> 1/f or, equivalently, Tex > 1. In order to check for the validity of the above conclusions, circuit simulations were carried out with reference to a low voltage deep sub-micron CMOS technology (0.12 μm) implementation of a differential amplifier. Values for VDD and VREF are respectively 1.5V and 0.7 V. A voltage buffer configuration has been chosen: R1 = R2 = R, with CMFB circuit assumed to have a unity gain. </span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiDgDAj29q4GY-WmRVwbEPnE-Q-3-s3gTu6LNc1JlAzsxLaWT0XwJug1_zl_S9bibPAZqdaRz23ypGT9f9-B2oCvjrCPF9Ip-elUP4ySdPFDyOwO4wKOLqRLxXlTZl7PHX0_J9wVSn6WuM/s1600/7.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="342" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiDgDAj29q4GY-WmRVwbEPnE-Q-3-s3gTu6LNc1JlAzsxLaWT0XwJug1_zl_S9bibPAZqdaRz23ypGT9f9-B2oCvjrCPF9Ip-elUP4ySdPFDyOwO4wKOLqRLxXlTZl7PHX0_J9wVSn6WuM/s400/7.bmp" width="400" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">The operating point ambiguity is apparent from analysis of the figure 5, which shows the CM static input-output characteristics of the open loop Opamp.</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgKNbQn8nyO04wRxW3_tK5bGffjJY6FL4NhpaNCvJzBmbaGeDuAKtlloypHLYDR9WcFlhOUgmSafdX3fuLs-QXbLdob5qnNOeO7SD2jXYUFQTDmEpag9TT1kd4Fb0-ThJo5N5dbAUAe9_E/s1600/8.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="291" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgKNbQn8nyO04wRxW3_tK5bGffjJY6FL4NhpaNCvJzBmbaGeDuAKtlloypHLYDR9WcFlhOUgmSafdX3fuLs-QXbLdob5qnNOeO7SD2jXYUFQTDmEpag9TT1kd4Fb0-ThJo5N5dbAUAe9_E/s400/8.bmp" width="400" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">A graphical estimation of k* from Fig.5, gives a value of 1.92, not too far from that obtained by manual analysis. Figure 6 shows the transient CM output voltage of the feedback amplifier corresponding to an input triangular signal V'icm. The output signal waveform can be derived from the static characteristic in Fig.5, since input signal frequency is small enough to be considered as a static stimulation. For V'icm approximately equal to 1.2 V, the d.c. amplifier output sets to: Vocm = VDD (point 3 in Fig.4). Once in this erroneus operating condition, the circuit is unable to exit even when V'icm settles to VREF. In fact, setting Vocm = VDD in equation (2), we obtain Vicm = 1.1V which falls outside the CM input dynamic range of the Opamp, corresponding (Fig.5) approximately to the interval [0, 0.9V]. Simulation (Fig.6) confirms that the circuit leaves the operating point 3 for V'icm = 0.3V, obtained by evaluating VREF in eq. (2) for Vicm = 0.9V and Vocm = VDD.</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg76ltKM8jYA959grWqiv0gCkCGLo5SceczO0Vbh0cV4jL4NmMySLs9_5qlA2QCdmAccwwApxgOvklyq8ngNCrB3Ggrpi37Wr3k27K5TgO0jroj2QnzeOx3HwevCGHp2D9j8IRwOczK7-k/s1600/9.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="321" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg76ltKM8jYA959grWqiv0gCkCGLo5SceczO0Vbh0cV4jL4NmMySLs9_5qlA2QCdmAccwwApxgOvklyq8ngNCrB3Ggrpi37Wr3k27K5TgO0jroj2QnzeOx3HwevCGHp2D9j8IRwOczK7-k/s400/9.bmp" width="400" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
<b style="color: #93c47d;">3. ALTERNATIVE CMFB TOPOLOGY</b><br />
<br />
A dissimilar CMFB topology is obtained by controlling the gate voltage across transistors M5- M6, rather than the Vgs of M0. Fig.7 shows the CM half circuit of the Miller Opamp of Fig.2 which employs the above CMFB topology. Evaluation of the internal CM loop gain Tint for the circuit in Fig.7 leads to the following expression:</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEinZZOGW77VFs1zCV3jIRQ3VulvKXqBoh8SK7STX6YxirVCN3IMZ8bcss4he2aYbG-QfRqb_AnADuj_c-HOwnpsgTixP5xeoM7b4e_6HpDlTrLamFoYOG6L2WnCOFkrhmVgTc85N4NuKt8/s1600/10.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="56" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEinZZOGW77VFs1zCV3jIRQ3VulvKXqBoh8SK7STX6YxirVCN3IMZ8bcss4he2aYbG-QfRqb_AnADuj_c-HOwnpsgTixP5xeoM7b4e_6HpDlTrLamFoYOG6L2WnCOFkrhmVgTc85N4NuKt8/s400/10.bmp" width="400" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">In contrast to the previous case, Tint is now independent from gm0, guaranteeing that Acm and, consequently Tex, are within a relatively low value even when high CM input voltage is applied which reduces gm0. The value of ACMFB can be chosen so as to obtain the desired value of Acm, even though it must also satisfy stability constraints referred to the internal CM loop. Reduction of Acm over a wider range of Vicm well above VREF results in the elimination of the instability condition since no multiple intersection points will be allowed in the plots of Fig.4. Circuit simulations were again carried out under the same conditions as in Figs. 5 and 6, but with the adoption of the second CMFB network, with results presented in Fig.8 and Fig.9. </span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgCn7OV0SGdShTGZw1h-L9vQcAAWU_F3XDPvsa3_trZmMlrEkxRvVHEY2GfsOobpaOCqtAlS-WQGMmiq6ZlxXQmd60b9xjrYBZdML_8syCqCeLpt5r18l2aLPqMNVadN_ydQXVQr6RVTT4/s1600/11.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="351" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgCn7OV0SGdShTGZw1h-L9vQcAAWU_F3XDPvsa3_trZmMlrEkxRvVHEY2GfsOobpaOCqtAlS-WQGMmiq6ZlxXQmd60b9xjrYBZdML_8syCqCeLpt5r18l2aLPqMNVadN_ydQXVQr6RVTT4/s400/11.bmp" width="400" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">Fig.8 shows that a single equilibrium point now exists for Vicm = 0.7 V. This result is also confirmed by transient analysis (Fig.9) since, in this case, the circuit does not enter an erroneous operating condition when stimulated with a full amplitude triangular waveform. However, for high values of the input signal, the output CM voltage Vocm drifts from its correct value, due to variation of the CM gain Acm, as is clearly in evidence looking at the slope of the solid line in Fig.8.</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhxXB1x74xwIzhrSO1OSfumBmva4Dw8QkkahsS15pllq8HvDpGQt5DiIuYX70G-Bl9h1spehgRprFCNhghV4H6l_lTXaSQh7XJ6QWoKcDSI8QLkV97ec3jCd43GLuVNUvKVCh8TvR5g0fQ/s1600/12.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="640" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhxXB1x74xwIzhrSO1OSfumBmva4Dw8QkkahsS15pllq8HvDpGQt5DiIuYX70G-Bl9h1spehgRprFCNhghV4H6l_lTXaSQh7XJ6QWoKcDSI8QLkV97ec3jCd43GLuVNUvKVCh8TvR5g0fQ/s640/12.bmp" width="419" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
<b style="color: #93c47d;">5. CONCLUSIONS</b><br />
<br />
This study shows that two distinct feedback loops are generally operating in a differential voltage amplifier with internal CMFB circuitry. The conditions under which their interaction does not allow for univocal determination of the d.c. operating point of the circuit have been identified. In particular, we related the presence of instability to the drop of the internal CM gain Tint for certain values of the input CM signal, which, in turn, increases the value of Acm and Tex. When comparison of the two different topologies of CMFB networks was carried out, only one solution was shown to be affected by instability. The validity of this analysis was checked by simulation with reference to deep submicron CMOS technology implementation.<br />
<br />
Hernández Caballero Indiana<br />
Asignatura: CAF<br />
Fuente:<a href="http://richpc1.ba.infn.it/~atauro/politecnico/publications/cr1141.pdf">http://richpc1.ba.infn.it/~atauro/politecnico/publications/cr1141.pdf</a></span></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-49042744304133423122010-07-25T23:27:00.002-04:302010-07-27T16:50:58.683-04:30A 403-MHz Fully Differential Class-E Amplifier in 0.35 μm CMOS for ISM Band Applications<h3 class="post-title entry-title"><a href="http://indianamaithe.blogspot.com/2010/07/403-mhz-fully-differential-class-e.html"></a> </h3><div class="post-header"></div><div style="text-align: justify;"><span style="font-size: small;"><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">Abstract</span></b><br style="font-family: Verdana,sans-serif;" /><br style="font-family: Verdana,sans-serif;" /> <span style="font-family: Verdana, sans-serif;">This paper presents the design and implementation of a low voltage, high efficiency class-E power amplifier (PA) for ISM band applications at 403 MHz. The PA circuit consists of an on-chip differential amplifier including the buffer stage on standard 0.35μm CMOS technology. The output matching circuit is implemented by off chip passive components including an external balun. The post-layout simulation results indicate that the amplifier is capable of delivering 20.9 dBm of output power to a 50Ω load with 1.5V power supply. The results also indicate that the PA has a gain of 11.8 dB at 403 MHz with power added efficiency (PAE) of 75%. The overall efficiencyincluding the buffer is 65.6%.</span><br style="font-family: Verdana,sans-serif;" /><br style="font-family: Verdana,sans-serif;" /><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">1. Introduction</span></b><br style="font-family: Verdana,sans-serif;" /> <br style="font-family: Verdana,sans-serif;" /><span style="font-family: Verdana, sans-serif;">The demand for single chip transceivers has motivated the design of power amplifiers in CMOS technology. Especially for short-range wireless applications that require moderate output power, CMOS amplifiers are the suitable choice. Various power amplifiers (PA) in CMOS technology have already been reported [1-4]. The mass fabrication cost of CMOS integrated circuits is relatively low; therefore, designing the whole system on a single chip is very cost effective. Considering the portable devices, an efficient power amplifier can provide long battery time. Therefore, increased efficiency is a prime requirement for future generation wireless systems. The major limitation with CMOS technology for high</span><span style="font-family: Verdana, sans-serif;"> power applications is its low breakdown voltage and especially the situation is worse with deep submicron CMOS devices. However, with advancements in technology and the availability of high voltage CMOS transistors, this problem can be addressed. Thus, for wireless applications, with moderate power, CMOS is an appropriate choice. In this paper, a differential power amplifier is designed and implemented using standard 0.35 μm CMOS technology process. The paper outline is as follows. Section 2 briefly describes the operation and design principles of class-E power amplifier. Section 3 discusses the design and implementation details of the amplifier circuit. Simulation results are provided in Section 4 while the work is concluded in Section 5.</span><br style="font-family: Verdana,sans-serif;" /><br style="font-family: Verdana,sans-serif;" /><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">2. Class-E operation</span></b><br style="font-family: Verdana,sans-serif;" /> <br style="font-family: Verdana,sans-serif;" /><span style="font-family: Verdana, sans-serif;">Switching power amplifiers theoretically achieve efficiencies as high as 100%, but have drawback of poor linearity. Such amplifiers are suitable for systems with constant envelope modulation schemes [5-6]. The class-E PA is the most attractive candidate in terms of circuit simplicity and high-frequency performance. Typical configuration of a Class-E power amplifier is shown in Figure 1.</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEijNU8ZGIppStQzOmlL8JtyzYwHPB7DDPtSCozVdKaI6QnBetCzdleFoeIgWzXlcTzJdgYm-7VZqmjiJinCKRuCw69JkKscosXwJuD_cnxZNitF9tZ41culAWbQWE9cxK8aoI0mZu06RaY/s1600/1.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="307" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEijNU8ZGIppStQzOmlL8JtyzYwHPB7DDPtSCozVdKaI6QnBetCzdleFoeIgWzXlcTzJdgYm-7VZqmjiJinCKRuCw69JkKscosXwJuD_cnxZNitF9tZ41culAWbQWE9cxK8aoI0mZu06RaY/s400/1.bmp" width="400" /></a></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span><br style="font-family: Verdana,sans-serif;" /><span style="font-family: Verdana, sans-serif;">Transistor M1 operates as a switch and its current is passed through an inductor called radio frequency choke (RFC). The capacitance CS is in parallel with M1 and the parasitic capacitance of transistor is included inCS . LFIL and CFIL comprise a tuned circuit in series with a reactive component jX and the load impedance Ropt . The switch is turned on and off periodically at the input frequency. The LFIL -CFIL filter is tuned to the first harmonic of the input frequency and only passes a sinusoidal current to the load Ropt. The reactive component jX introduces the appropriate phase shift between the output voltage and the switch voltage to obtain desired waveforms [7]. The load network is designed such that the voltage across the switch is kept low when the switch turns off and voltage across the switch is zero when the switch turns on. The component values of single ended class-E power amplifier can be computed by following set of equations [8-10]: </span></span></div><div style="text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj9gZR4VxN04Pzyb1Y2MpA-JFNjQZ7lj5tYDoOScl26lh0Mrtgkn6P3psgE2Qr5mwWK-sZdNXGq3ua3m580NikmFEjXjp0Y4MenjgXmJnwQtjLxcVtVo_0lcSZ_Mcb7xt8-lkWBnPeplZs/s1600/2.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="231" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj9gZR4VxN04Pzyb1Y2MpA-JFNjQZ7lj5tYDoOScl26lh0Mrtgkn6P3psgE2Qr5mwWK-sZdNXGq3ua3m580NikmFEjXjp0Y4MenjgXmJnwQtjLxcVtVo_0lcSZ_Mcb7xt8-lkWBnPeplZs/s400/2.bmp" width="400" /></a></div><div style="text-align: justify;"></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Where VDD, Pout, ω, and Q are PA supply voltage, PA output power, PA resonant frequency and inductor Q factor respectively.</span><br style="font-family: Verdana,sans-serif;" /> <br style="font-family: Verdana,sans-serif;" /><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">3. Design & Implementation</span></b><br style="font-family: Verdana,sans-serif;" /><br style="font-family: Verdana,sans-serif;" /> <span style="font-family: Verdana, sans-serif;">The major limitation of the CMOS technology is low breakdown voltage (VDS). In class-E amplifiers, the stress voltage at drain is 3.6 times VDD, therefore it is necessary to choose a device with higher VDS. For our design, we have chosen a high voltage NMOS transistor from standard 0.35μm CMOS design kit. This transistor has a maximum break down voltage of VDS=5.5V, and hence, with 1.5V VDD the maximum stress voltage on drain of the transistor is within safe limits, i.e., 5.4V.</span><br style="font-family: Verdana,sans-serif;" /><br style="font-family: Verdana,sans-serif;" /><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">3.1. Single ended class-E design</span></b><br style="font-family: Verdana,sans-serif;" /> <br style="font-family: Verdana,sans-serif;" /><span style="font-family: Verdana, sans-serif;">A single ended Class-E amplifier is shown in Figure 2. The circuit was optimized for an output power of 150 mW with an operating frequency of 403 MHz at a supply voltage of 1.5V. Simulation results indicate that the transistor width of 1800 μm is required in order to meet the output power requirements. The other component values were computed by (1-5) and finally optimized by CAD simulations.</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg46rj61pcepw2LOeWPLAb9gVCYjm4FierqI_SgemRS-hIEI2f0CGTMlMbVSfoY1LusK4dFKY40koEgH_0mWpbCeWng-Vr-_YJEHH-N5qfUZK-q9VLC0LBLeWtbpcLuGUyzXsynp8-Uubk/s1600/3.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="290" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg46rj61pcepw2LOeWPLAb9gVCYjm4FierqI_SgemRS-hIEI2f0CGTMlMbVSfoY1LusK4dFKY40koEgH_0mWpbCeWng-Vr-_YJEHH-N5qfUZK-q9VLC0LBLeWtbpcLuGUyzXsynp8-Uubk/s400/3.bmp" width="400" /></a></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span><br style="font-family: Verdana,sans-serif;" /><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">3.2. Differential class-E design</span></b><br style="font-family: Verdana,sans-serif;" /> <br style="font-family: Verdana,sans-serif;" /><span style="font-family: Verdana, sans-serif;">Using differential topology gives some benefits over single ended configuration, such as common mode noise suppression. As a consequence, the even order harmonics are not significant. Differential design doubles the output power when compared with a single ended amplifier. For the same supply voltage and output power, the requirement on transistor size is also reduced in differential designs. This produces less parasitic capacitances and relaxes current consumption of the amplifier. Figure 3 shows the schematic of differential amplifier. The large inductors LRFC and LFIL are implemented off chip along with the external balun.</span></span></div><div style="text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh7cgr7QqJROHDS99qlYMCGdthUoQhr0W73MocEeJ76ltMAlzPWaRgNoCUVCFoeOvHh29VTKsY2mkmQ38ltz8mF66xtJyJ1l7yGXDIvMfAfRQW_LmtVORYwT8ao8na_jTaWX3bHPbZJBGs/s1600/4.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="327" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh7cgr7QqJROHDS99qlYMCGdthUoQhr0W73MocEeJ76ltMAlzPWaRgNoCUVCFoeOvHh29VTKsY2mkmQ38ltz8mF66xtJyJ1l7yGXDIvMfAfRQW_LmtVORYwT8ao8na_jTaWX3bHPbZJBGs/s400/4.bmp" width="400" /></a></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span><br style="font-family: Verdana,sans-serif;" /><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">3.3. Buffer design</span></b><br style="font-family: Verdana,sans-serif;" /> <br style="font-family: Verdana,sans-serif;" /><span style="font-family: Verdana, sans-serif;">The width of amplifier transistor is as large as 1800 μm that produces high parasitic capacitances. Consequently, the input gate capacitance Cgs of the transistor becomes too large to be driven by the preceding stage of the amplifier. A buffer amplifier, in such cases is required to drive the amplifier. The buffer is designed by a chain of inverters connected in series to drive the large capacitive load of 6.864 pF. Each inverter is larger by a factor of K (tapering factor) than the preceding inverter. For known input and output capacitive loads, the optimum value of Kopt and total number of inverter stages required in the buffer chain can be determined. The input gate capacitance CL of the amplifier transistor is 6.864 pF. Total input capacitance of first inverter stage is 4 fF and the output capacitance of first inverter stage (unloaded) is 1.8 fF. Optimum number of inverter buffer stages N is calculated and results in N=6.7. A seven stage buffer is required to drive a load capacitance of 6.864 pF. However, the simulation results indicate that only a five stage buffer is sufficient as it does not degrade the performance. Sizes of each stage's PMOS and NOMS transistors are tabulated in Table 1.</span></span></div><div style="text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh23-9lkOL9r6lZZsaq7V_beS805I-llp0S4AVxsPR-crLUMpN-N0brGjK5OEwplqjOWcyXz1UepcdtVuxdxUrxS3Z49pNOw6u4YG3-iadnmWSaQ1n3gUtD4-4Kt1b1pG78uc4fxmqn03I/s1600/5.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="126" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh23-9lkOL9r6lZZsaq7V_beS805I-llp0S4AVxsPR-crLUMpN-N0brGjK5OEwplqjOWcyXz1UepcdtVuxdxUrxS3Z49pNOw6u4YG3-iadnmWSaQ1n3gUtD4-4Kt1b1pG78uc4fxmqn03I/s400/5.bmp" width="400" /></a></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span><br style="font-family: Verdana,sans-serif;" /><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">3.4. Layout issues</span></b><br style="font-family: Verdana,sans-serif;" /> <br style="font-family: Verdana,sans-serif;" /><span style="font-family: Verdana, sans-serif;">On-chip realization of inductors LRFC and LFIL is not feasible as it occupies a large chip area. Therefore, external high Q inductors were used. The bond wire inductance is also taken into account. In differential architecture, the symmetry of on-chip components and dimensions of the interconnects play a very vital role in the performance to cater process variation. Since the design is a differential, it has two identical single ended circuits. The PA has potentially large currents in different parts of circuit, so wide and stacked interconnect structures are used. Transistors in the circuit have large sizes such as widths of 1800 μm. It is not viable to place such a large transistor in one dimension, as poly material has high resistivity than metal and becomes too resistive over long dimensions. Multi-fingers were used and folded for carving large transistors. The poly materials of the fingers are connected in parallel to significantly reduce the resistance. All drains of multi-fingers are interconnected to behave as one single drain. In a similar way, all sources are interconnected to provide one single source. To avoid cross-talk and interference at radio frequencies, different blocks are encapsulated with guard-rings. This helps isolating the blocks to minimize interference and decouple substrate noise. Adequate on-chip decoupling capacitors were also used. The layout for the differential amplifier is shown in Figure 4. The overall chip area is 0.56 mm2 (700x800 μm) including the pads.</span></span></div><div style="text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhS4PTYAPmDlvr1dRSrNZqWL_N4pMLovgKmVDpnKb3RA3gJ6cLuCl8uZIN8dyffCMaOfMka9EbOP7tmRq6y4NFc4h8iEYK_JXVKaXxh71IF5Z8kdDXBDbPaYg8n_-eRsfG-p6rooipRKss/s1600/6.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="313" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhS4PTYAPmDlvr1dRSrNZqWL_N4pMLovgKmVDpnKb3RA3gJ6cLuCl8uZIN8dyffCMaOfMka9EbOP7tmRq6y4NFc4h8iEYK_JXVKaXxh71IF5Z8kdDXBDbPaYg8n_-eRsfG-p6rooipRKss/s320/6.bmp" width="320" /></a></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span><br style="font-family: Verdana,sans-serif;" /><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">4. Simulation results</span></b><br style="font-family: Verdana,sans-serif;" /> <br style="font-family: Verdana,sans-serif;" /><span style="font-family: Verdana, sans-serif;">The circuit simulations were performed in Cadence®. A test bench is designed to simulate the performance of PA. Pre and post-layout simulations were carried out. </span></span></div><div style="text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglW5QKeJS5vhbYL09k6qFZBxPIuuok1KEwi56JC7OIrqwI6AXfIHLZ_xIn2ulPBMHSqTciajOGw-1QKsKoTBnAJI0lMrExPi0q0-iZo_xurCTbo6TtL7xUCGy_dq1_StJOmAaPO1cNHXE/s1600/7.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="302" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglW5QKeJS5vhbYL09k6qFZBxPIuuok1KEwi56JC7OIrqwI6AXfIHLZ_xIn2ulPBMHSqTciajOGw-1QKsKoTBnAJI0lMrExPi0q0-iZo_xurCTbo6TtL7xUCGy_dq1_StJOmAaPO1cNHXE/s400/7.bmp" width="400" /></a></div><div style="text-align: justify;"></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 5 shows waveforms at different nodes of the class-E PA after post layout simulations with RC extraction. Results indicate that the amplifier has a gain of 11.8 dB at 403MHz. Figure 6 shows power added efficiency (PAE) and output power as a function of input frequency. At 403 MHz, PAE of the PA is 75% and the output power is 125 mW. The overall efficiency including the buffer stage is 65.6%.</span></span></div><div style="text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhntfgcw_o9ockxPyRUhAuACWgGzYJhUygBcm1s-MHDEi19ttYTmR3vUfkQVP9J_C-0HHyJCUhdOrnUelGYWx5BIo2-HjhIJB7tp2c4jeKHoH1cW0RCYS50oRD4GGVhzw3gdEBlFVRtsPg/s1600/8.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="301" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhntfgcw_o9ockxPyRUhAuACWgGzYJhUygBcm1s-MHDEi19ttYTmR3vUfkQVP9J_C-0HHyJCUhdOrnUelGYWx5BIo2-HjhIJB7tp2c4jeKHoH1cW0RCYS50oRD4GGVhzw3gdEBlFVRtsPg/s400/8.bmp" width="400" /></a></div><div style="text-align: justify;"><span style="font-size: small;"><br style="font-family: Verdana,sans-serif;" /><span style="font-family: Verdana, sans-serif;">Table 2 shows the comparison of results with already reported similar power amplifiers.</span></span></div><div style="text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjwHcvXOQB09SL6bdz8MhZumAr1PwDekpkjs9B5kRzibBCKydAFuQkPwSdKLBV0qLZN25_r5lGw1KPiMgDPax1O-mqDskvp0JQHnqgKyYAFtJgqH3Ci8zY2T2BFee2HpSYoIyLnBK0E4HM/s1600/9.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="232" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjwHcvXOQB09SL6bdz8MhZumAr1PwDekpkjs9B5kRzibBCKydAFuQkPwSdKLBV0qLZN25_r5lGw1KPiMgDPax1O-mqDskvp0JQHnqgKyYAFtJgqH3Ci8zY2T2BFee2HpSYoIyLnBK0E4HM/s400/9.bmp" width="400" /></a></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span><br style="font-family: Verdana,sans-serif;" /><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">5. Conclusion</span></b><br style="font-family: Verdana,sans-serif;" /> <br style="font-family: Verdana,sans-serif;" /><span style="font-family: Verdana, sans-serif;">The design and implementation of a low voltage high efficiency fully differential class-E amplifier is presented. Some key implementation issues have also been discussed. The post-layout simulation results are encouraging and indicate that the amplifier has potential to deliver 20.9 dBm of output power to a 50Ω load with 1.5V power supply. The results also indicate that the amplifier has a gain of 11.8 dB at 403 MHz with power added efficiency (PAE) of 75%. The overall efficiency including the buffer is 65.6%.</span><br style="font-family: Verdana,sans-serif;" /><br style="font-family: Verdana,sans-serif;" /><span style="font-family: Verdana, sans-serif;">Hernández Caballero Indiana</span><br style="font-family: Verdana,sans-serif;" /> <span style="font-family: Verdana, sans-serif;">Asignatura: CAF</span><br style="font-family: Verdana,sans-serif;" /><span style="font-family: Verdana, sans-serif;">Fuente:<a href="http://www.ewdtest.com/conf/proc08/ewdts08-68.pdf">http://www.ewdtest.com/conf/proc08/ewdts08-68.pdf</a></span></span></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-9718750762472366662010-07-25T23:26:00.002-04:302010-07-27T16:50:36.149-04:30A NOVEL FULLY-DIFFERENTIAL CLASS AB FOLDEDCASCODE OTA FOR SWITCHED-CAPACITOR APPLICATIONS<div class="post-header"></div><div class="post-body entry-content"><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_filelist.xml" rel="File-List"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_themedata.thmx" rel="themeData"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_colorschememapping.xml" rel="colorSchemeMapping"></link> <style>
<!-- /* Font Definitions */ @font-face {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4; mso-font-charset:0; mso-generic-font-family:roman; mso-font-pitch:variable; mso-font-signature:-1610611985 1107304683 0 0 159 0;} @font-face {font-family:Calibri; panose-1:2 15 5 2 2 2 4 3 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:-1610611985 1073750139 0 0 159 0;} @font-face {font-family:Verdana; panose-1:2 11 6 4 3 5 4 4 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:536871559 0 0 0 415 0;} @font-face {font-family:TimesNewRomanPSMT; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:131 0 0 0 9 0;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {mso-style-unhide:no; mso-style-qformat:yes; mso-style-parent:""; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:0cm; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} a:link, span.MsoHyperlink {mso-style-priority:99; color:blue; mso-themecolor:hyperlink; text-decoration:underline; text-underline:single;} a:visited, span.MsoHyperlinkFollowed {mso-style-noshow:yes; mso-style-priority:99; color:purple; mso-themecolor:followedhyperlink; text-decoration:underline; text-underline:single;} p.MsoListParagraph, li.MsoListParagraph, div.MsoListParagraph {mso-style-priority:34; mso-style-unhide:no; mso-style-qformat:yes; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:36.0pt; mso-add-space:auto; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} p.MsoListParagraphCxSpFirst, li.MsoListParagraphCxSpFirst, div.MsoListParagraphCxSpFirst {mso-style-priority:34; mso-style-unhide:no; mso-style-qformat:yes; mso-style-type:export-only; margin-top:0cm; margin-right:0cm; margin-bottom:0cm; margin-left:36.0pt; margin-bottom:.0001pt; mso-add-space:auto; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} p.MsoListParagraphCxSpMiddle, li.MsoListParagraphCxSpMiddle, div.MsoListParagraphCxSpMiddle {mso-style-priority:34; mso-style-unhide:no; mso-style-qformat:yes; mso-style-type:export-only; margin-top:0cm; margin-right:0cm; margin-bottom:0cm; margin-left:36.0pt; margin-bottom:.0001pt; mso-add-space:auto; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} p.MsoListParagraphCxSpLast, li.MsoListParagraphCxSpLast, div.MsoListParagraphCxSpLast {mso-style-priority:34; mso-style-unhide:no; mso-style-qformat:yes; mso-style-type:export-only; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:36.0pt; mso-add-space:auto; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoPapDefault {mso-style-type:export-only; margin-bottom:10.0pt; line-height:115%;} @page Section1 {size:612.0pt 792.0pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} /* List Definitions */ @list l0 {mso-list-id:1436629036; mso-list-type:hybrid; mso-list-template-ids:-1370584154 201981967 201981977 201981979 201981967 201981977 201981979 201981967 201981977 201981979;} @list l0:level1 {mso-level-tab-stop:none; mso-level-number-position:left; text-indent:-18.0pt;} ol {margin-bottom:0cm;} ul {margin-bottom:0cm;} -->
</style> <br />
<div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><b><span lang="EN-US" style="font-family: Verdana, sans-serif; font-size: 12pt;"></span></b></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"></span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><b><span lang="EN-US" style="font-family: Verdana, sans-serif;"><span style="color: #93c47d;">ABSTRACT</span></span></b></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span lang="EN-US" style="font-family: Verdana, sans-serif;">This paper presents a new single-stage fully-differential class AB folded-cascode operational transconductance amplifier (OTA) for low-voltage and fast-settling switched-capacitor circuits in pure digital CMOS technology. The proposed OTA employs class AB operation in both the input-stage and output current source transistors resulting in large slew rate, enhanced unity-gain bandwidth and DC gain. The method to build the class AB operation in the output current source transistors is very simple which does not need any extra circuit and power consumption. HSPICE simulation results are presented to show the usefulness of the proposed OTA's structure.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoListParagraphCxSpFirst" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify; text-indent: -18pt;"><span style="font-size: x-small;"><b style="color: #93c47d;"><span lang="EN-US" style="font-family: Verdana, sans-serif;">1.<span style="font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; line-height: normal;"> </span></span></b><b><span lang="EN-US" style="font-family: Verdana, sans-serif;"><span style="color: #93c47d;">INTRODUCTION</span></span></b></span></div><div class="MsoListParagraphCxSpLast" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span lang="EN-US" style="font-family: Verdana, sans-serif;">Design of high performance analog circuits is becoming increasingly challenging with the persistent trend toward reduced supply voltages. The main bottleneck in analog circuits is the operational amplifier. Operational amplifiers are widely employed to drive large capacitive loads in many switched-capacitor applications such as the integrators, gain stages, etc. For high speed applications, fast-settling OTAs are required, which demand both high unity-gain bandwidth and slew rate. In class A OTAs the slew rate is limited by the bias currents. For example in folded-cascode OTA assuming equal currents of <i>Ib </i>in both input and cascode transistors, the slew rate can be considered as <i>SR </i>= 2<i>Ib</i>/<i>CL</i>, where <i>CL </i>is the load capacitor. So, a trade-off exists between the static power dissipation and the slewing behavior of a class A OTA. However, in class AB OTAs the slew rate is not limited by the quiescent currents since when a large input signal is applied, large currents are generated provided that the circuit is designed properly. In this paper a single-stage class AB folded-cascode OTA which employs class AB operation in both the input-stage and output current source transistors is proposed which results in large slew rate. This technique also enhances the OTA's unity gain bandwidth and DC gain. Section (2) presents the proposed OTA structure. In section (3) circuit simulation results are discussed. Finally, conclusions are presented in section (4).</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoListParagraphCxSpFirst" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify; text-indent: -18pt;"><span style="font-size: x-small;"><b style="color: #93c47d;"><span lang="EN-US" style="font-family: Verdana, sans-serif;">2.<span style="font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; line-height: normal;"> </span></span></b><b><span lang="EN-US" style="font-family: Verdana, sans-serif;"><span style="color: #93c47d;">PROPOSED OTA TOPOLOGY</span></span></b></span></div><div class="MsoListParagraphCxSpLast" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span lang="EN-US" style="font-family: Verdana, sans-serif;">Figure 1 shows the proposed OTA structure. It employs the class AB operation in both input-stage and output current source transistors. To build the input-stage class AB operation, the proposed OTA uses two matched input transistors M1 and M2 cross-coupled by two constant voltage sources generated by two flipped voltage follower (FVF) cells acting as DC level shifters [1, 2, 6]. FVF cells composed of Mc1-Mc6 are used to build the floating voltage sources due to their very low output resistance instead of the conventional common drain structures [3]. Under quiescent conditions, i.e. when no input signal is applied, the gate voltage of input transistors M1 and M2 is the same. In this case, V<i>SG</i>1 = V<i>SG</i>2 = Vb, and both transistors carry equal currents which are controlled by Vb. Vb can be chosen slightly greater than the MOS threshold voltage which results in low quiescent currents. When an input signal is applied, a large current is generated in one of the input transistors. If for instance vin+ increases and vin- decreases, the source voltage of M2 increases whereas the voltage at the source of M1 decreases by the same amount. So, the drain current of M1 decreases while the drain current of M2 increases. Hence, the maximum current of M1 and M2 is independent of quiescent current when an input signal is applied. To build the class AB operation in the output current source transistors, the gates of M9 and M10 are connected to those of Mc6 and Mc5, respectively, which results in large currents to flow during the slewing in one of cascade branches. If for instance, vin+ is greater than vin-, the drain current of M1 will be decreased while the drain current of M2 will be increased by the same amount. The drain current of Mc5 will be increased, and so M10, while the drain current of Mc6 and M9 will be decreased. On the other hand, it can be also explained that the gate voltage of M3 and M4, cmfb, will be increased due to the sudden increment of the drain current and voltage of M2 through coupling of the gate-drain capacitor of M4 as it is seen in Fig. 2(a). The drain voltage of M2 increases greatly due to the enhancement of its drain current which results in raising the gate voltage of M3 and M4 through the gatedrain capacitance of M4. So, the drain current of M3 and M4 will be increased as shown in Fig. 2(b). Hence, the current of M10 will be forced to the positive output node, vout+, and the negative output node will be discharged by the current of M3. It is worth to mention that the increased drain current of M4 will be provided by M2 since due to the sudden increment of drain voltage of M2, the transistor M6 will be forced to cut-off. A similar improvement in the value of slew rate is obtained when a large negative input signal is applied to the proposed OTA. Therefore, a large slew rate will be obtained during both the positive and negative OTA's slewings.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span lang="EN-US" style="font-family: Verdana, sans-serif;"></span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span lang="EN-US" style="font-family: Verdana, sans-serif;"></span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgCEUq_z9srJlbals9WoxJjYMBmrKzOBiKDdDcrN1vGmqDJAzzXNCDAPlt1C786zVoop6rb8X1BBTVMjUhyphenhyphenEacVA2xUVMLLmx_7gce5_a0H6joeoTonK9l8ApP4dQTEwJUc18p4Smla3Xw/s1600/1.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="296" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgCEUq_z9srJlbals9WoxJjYMBmrKzOBiKDdDcrN1vGmqDJAzzXNCDAPlt1C786zVoop6rb8X1BBTVMjUhyphenhyphenEacVA2xUVMLLmx_7gce5_a0H6joeoTonK9l8ApP4dQTEwJUc18p4Smla3Xw/s400/1.bmp" width="400" /></a></span></div><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span lang="EN-US" style="font-family: Verdana, sans-serif;">If the gates of M9 and M10 are connected to a fixed bias voltage, their currents will be remained fixed during the OTA's slewing. In this case, when a large positive input signal is applied to the OTA, the positive output node will be charged only by the DC bias current of M10. So, the slew-rate of the proposed OTA will be much larger than that of folded-cascode OTA which employs class AB operation only in its input transistors. The class AB operation of output current source transistors, M9 and M10, also enhances the OTA's small signal DC gain and unity-gain bandwidth. When a small signal is applied to the OTA's input, this signal also appears across the gate-source of output current source transistors, M9 and M10 through the FVF buffer cells, which in turn results in enhancing the DC gain of OTA. Also the effective transconductance of the input transistors are increased from <i>gm</i>1,2 to about <i>gm</i>1,2 + <i>gm</i>9,10 which enhances the OTA's unity-gain bandwidth by the same amount. It is worth mentioning that the class AB operation of the input-stage results in doubling the effective transconductance of input transistors, and hence doubling the unity-gain bandwidth and DC gain.</span><br />
<span lang="EN-US" style="font-family: Verdana, sans-serif;"></span></span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi42F2hhQlxkqcxYkrVGSUmnLcbRdo0QRZ4caNcmu87Lyh46ujuO-QX3WaYZz7dqJQqkJHvN5mp2CjBa0ZiDB2sPcsPVb86UO9ttDtTIKgAdj2r0QUc6rj_FnWmUEV5jj8khOzOHx1AhK8/s1600/2.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi42F2hhQlxkqcxYkrVGSUmnLcbRdo0QRZ4caNcmu87Lyh46ujuO-QX3WaYZz7dqJQqkJHvN5mp2CjBa0ZiDB2sPcsPVb86UO9ttDtTIKgAdj2r0QUc6rj_FnWmUEV5jj8khOzOHx1AhK8/s400/2.bmp" width="272" /></a></span></div><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span lang="EN-US" style="font-family: Verdana, sans-serif;">The proposed OTA has the lowest power supply voltage requirement which is about V<i>GS </i>+ V<i>eff </i>where V<i>eff </i>is the drain-source saturation voltage of an MOS transistor. To get a large output signal swing, a two-stage OTA can be utilized where the first stage can be the proposed OTA in this paper and the second stage is a common-source topology with a class AB operation. Cascode compensation and/or hybrid cascode compensation can be used to stabilize this two-stage OTA in fast-settling applications [4]. A simple switched-capacitor common mode feedback (CMFB) circuit such as proposed in [5] is used to define the common-mode voltage of output nodes of the proposed OTA.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoListParagraphCxSpFirst" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify; text-indent: -18pt;"><span style="font-size: x-small;"><b style="color: #93c47d;"><span lang="EN-US" style="font-family: Verdana, sans-serif;">3.<span style="font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; line-height: normal;"> </span></span></b><b><span lang="EN-US" style="font-family: Verdana, sans-serif;"><span style="color: #93c47d;">SIMULATION RESULTS</span></span></b></span></div><div class="MsoListParagraphCxSpLast" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span lang="EN-US" style="font-family: Verdana, sans-serif;">To verify the usefulness of the proposed OTA, it was designed using a 0.25</span><span style="font-family: Verdana, sans-serif;">μ</span><span lang="EN-US" style="font-family: Verdana, sans-serif;">m BSIM3v3 level 49 mixed-signal CMOS models with HSPICE for a switched-capacitor integrator with sampling and integrating capacitors of 2.5- pF and 10-pF, respectively. The load capacitance was 10- pF and 7.5-pF in AC open loop and transient closed loop simulations, respectively. The designed device sizes and circuit parameters are shown in Table 1. Figure 3 shows the frequency response of the proposed OTA including the conventional folded-cascode OTA called OTA1 here and the folded-cascode OTA with class AB operation only in its input-stage called OTA2 here. The settling performance of all three simulated OTAs is shown in Fig. 4. A summary of the simulation results is shown in Table 2. In these simulations, equal values for the transistors' dimensions and bias currents have been used. Simulation results show that the proposed OTA achieves unity-gain bandwidth of about three times that of the conventional folded-cascode (OTA1) and about two times that of the folded-cascode OTA employing class AB operation only in its input-stage (OTA2). Its settling time is much less than the other two topologies due to its large slew rate and also unity-gain bandwidth. The proposed OTA also achieves about 3.6-dB and 10-dB DC gain greater than the class AB input-stage and conventional folded-cascode OTAs, respectively. The slew rate of class AB input-stage OTA is about the same as that of the conventional folded-cascode since when a positive input signal is applied, its positive output node is charged only by the bias current of M10.</span><br />
<br />
</span> <br />
<div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiV16z5NIbIdEiNQOUl9bHJfu7JIjszeFyqVga9n7awsmHjxMeEFJExCsd6w0HQiF2EwABSNnO0adov2BgQgGau0RvnYwgl9ZGn-SVDJkJ4BYG9wrltw53m47ubqt3RZHz9sLIOX6Su9h8/s1600/3.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="261" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiV16z5NIbIdEiNQOUl9bHJfu7JIjszeFyqVga9n7awsmHjxMeEFJExCsd6w0HQiF2EwABSNnO0adov2BgQgGau0RvnYwgl9ZGn-SVDJkJ4BYG9wrltw53m47ubqt3RZHz9sLIOX6Su9h8/s400/3.bmp" width="400" /></a></span></div><span style="font-size: x-small;"><br />
<span lang="EN-US" style="font-family: Verdana, sans-serif;"></span></span> <span style="font-size: x-small;"><br />
<span lang="EN-US" style="font-family: Verdana, sans-serif;"></span></span> <span style="font-size: x-small;"><br />
<span lang="EN-US" style="font-family: Verdana, sans-serif;"></span></span> </div><div class="MsoListParagraphCxSpFirst" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify; text-indent: -18pt;"><span style="font-size: x-small;"><b style="color: #93c47d;"><span lang="EN-US" style="font-family: Verdana, sans-serif;">4.<span style="font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; line-height: normal;"> </span></span></b><b><span lang="EN-US" style="font-family: Verdana, sans-serif;"><span style="color: #93c47d;">CONCLUSION</span></span></b></span></div><div class="MsoListParagraphCxSpLast" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span lang="EN-US" style="font-family: Verdana, sans-serif;">In this paper a novel fully-differential class AB foldedcascode OTA was proposed. The proposed OTA topology offers enhanced slew rate, unity-gain bandwidth, and DC gain by employing a simple technique to build the class AB operation in the output current source transistors in addition to using the conventional class AB input-stage. The method to build the class AB operation in the output current source transistors is simply realized by proper connection between the input-stage and the output stage nodes with no extra transistors and power dissipation.</span><br />
<br />
</span> <br />
<div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEin1RaJGH1HHyo8bRiThefBq-zOrPo1rq4xeI3YfpmOIsCpgMtnUNI9M_j8VgZ8MPhyphenhyphenfAmahgmkt6l3T14pCCozpezhyphenhyphencjOXPBpmsCqLU3IGXjflPEq9S75MwCU1nxl-nK21gBPvH5jFTM/s1600/4.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="640" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEin1RaJGH1HHyo8bRiThefBq-zOrPo1rq4xeI3YfpmOIsCpgMtnUNI9M_j8VgZ8MPhyphenhyphenfAmahgmkt6l3T14pCCozpezhyphenhyphencjOXPBpmsCqLU3IGXjflPEq9S75MwCU1nxl-nK21gBPvH5jFTM/s640/4.bmp" width="292" /></a></span></div><span style="font-size: x-small;"><br />
</span> <br />
<div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhUpmiiemd55gSogxz-MeoEcdBNns3hZrRR50AADAoS0VTVISCViXCbOH6rLYgqkeGDXNMA3j0oM9k8T3hcs0daSluyGCWDdZFsZuV15bo5S5XqcvWo3JqdciPDDw7_vEtEIFEk9WGtlgk/s1600/5.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="216" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhUpmiiemd55gSogxz-MeoEcdBNns3hZrRR50AADAoS0VTVISCViXCbOH6rLYgqkeGDXNMA3j0oM9k8T3hcs0daSluyGCWDdZFsZuV15bo5S5XqcvWo3JqdciPDDw7_vEtEIFEk9WGtlgk/s400/5.bmp" width="400" /></a></span></div><span style="font-size: x-small;"><br />
<span lang="EN-US" style="font-family: Verdana, sans-serif;"></span></span> <span style="font-size: x-small;"><span lang="EN-US" style="font-family: Verdana, sans-serif;"></span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Hernández Caballero Indiana</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Asignatura: CAF</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Fuente:</span><span style="font-family: Verdana, sans-serif;"><a href="http://eng.ut.ac.ir/iclab/members/yavari/Papers/ICEE%2705_Yavari.pdf">http://eng.ut.ac.ir/iclab/members/yavari/Papers/ICEE%2705_Yavari.pdf</a></span></span></div></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-5698850694127124402010-07-25T23:23:00.002-04:302010-07-27T16:50:05.814-04:30A Differential Switched-Capacitor Amplifier with Programmable Gain and Output Offset Voltage<h3 class="post-title entry-title"><a href="http://indianamaithe.blogspot.com/2010/07/differential-switched-capacitor.html"></a> </h3><div class="post-header"></div><div style="text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;"></span></div><div style="text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;"><b style="color: #93c47d;">ABSTRACT</b><br />
<br />
The design of a low-power differential switched-capacitor amplifier for processing a fully-differential input signal coming from a pressure sensor interface is reported. The circuit is intended to amplify the input signal, convert it to single-ended mode and shift its output by an offset voltage. The gain and output offset voltage are digitally programmable. The differential switched-capacitor amplifier employs an op amp voltage cancellation technique without requiring its output to slew to analog ground each time the amplifier is reset. Additionally, the circuit topology is very insensitive to low op amp gain and allows to attain 9-bit linearity. Moreover, a switched-capacitor commonmode feedback configuration with symmetric loading of the differential mode loop has been adopted to reduce charge injection and leakage current errors as well as to settle much faster than traditional CMFB circuits. The circuit has been successfully integrated into a SoC device where, after the analog preprocessing, the pressure sensor signal is measured through a 10- bit ADC. Implemented in a standard 4-metal single-poly 0.25um CMOS process, the module occupies a silicon area of 0.115 mm2, operates down to 1.8V and its 3-V typical current consumption is 40uA.<br />
<br />
<b style="color: #93c47d;">1. INTRODUCTION</b><br />
<br />
The continuous increase in System-on-Chip (SoC) complexity has been placing strong constraints to analog Intellectual Proprietary (IP) design. Although SoCs are usually targeted to digital-tailored technologies for financial reasons, they frequently demand lowpower low-voltage high-accuracy analog IPs. One way to overcome these conflicting requirements is the use of Switched-Capacitor (SC) circuits. Switched-capacitor technique efficiently compensates input offset and finite gain errors inherent to operational amplifiers (op amps). Moreover, due to its purely capacitive load, op amps do not require a high-power output driver, reducing area and power consumption as well as greatly simplifying frequency compensation as the load capacitance itself compensates the op amp. Finally, high accuracy and programmability are achieved with careful design and layout of capacitor ratios. The circuit presented herein is a low-power switched-capacitor amplifier implemented with metal (MiM) capacitors to achieve high linearity and device matching. Its architecture is described in Section 2 while Section 3 addresses its main design considerations. Experimental results are summarized in Section 4 followed by the final conclusions in Section 5.<br />
<br />
<b style="color: #93c47d;">2. CIRCUIT DESCRIPTION</b><br />
<br />
Fig. 1 illustrates a block diagram of the Differential Amplifier (DA). It is composed by 2 stages. First stage amplifies the differential input signal by 16 allowing ±25% of digital trimming. The second stage is a differential-to-single-ended, unity gain stage that adjusts the DC output level by adding an offset voltage programmable within ±25% using 2 trimming bits. Both gain and offset trimming add active calibration capability to the Differential Amplifier through the 10-bit Analog-to-Digital Converter (ADC). Hence any deviations in gain and offset can be stored in internal SoC registers for later software compensation. The Differential Amplifier control signals (clock, enable, test enable and ADC trigger) properly synchronizes the circuit with the pressure sensor and the AD converter. The DA amplifies the input signal and adds an offset voltage to the output. Both gain and offset are functions of capacitor ratios. The mathematical description of the output voltage (derived from Fig. 2 and Fig. 5) is given by: </span><br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjGB9bppsJ4IXZ4gOkGs0V9TSM8CRRnMYklpRHhc7mKaIMV0oIRnyGWa6mqfeVanKSUjLy5TD9uuR-liIafb8C4pEBzvx3shyMfpFYoBWPpEmB9GBVPUDWeZkDp1RWGyMz7-wb3JTs-J00/s1600/111.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="212" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjGB9bppsJ4IXZ4gOkGs0V9TSM8CRRnMYklpRHhc7mKaIMV0oIRnyGWa6mqfeVanKSUjLy5TD9uuR-liIafb8C4pEBzvx3shyMfpFYoBWPpEmB9GBVPUDWeZkDp1RWGyMz7-wb3JTs-J00/s400/111.bmp" width="400" /></a></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEghc6cRKpip4gN442R-T9VFsKnbclN5gWMN_ZeMH22YnKCdZ9j94AKWSaEVSuANgyXGknHH76SSDSx-1jCXwhYg0Rmj3R2N9hVYo0slWgfuwA8Y7-C2XRN0gcRS66c5rqt7eqyvV7LWTHM/s1600/2.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="56" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEghc6cRKpip4gN442R-T9VFsKnbclN5gWMN_ZeMH22YnKCdZ9j94AKWSaEVSuANgyXGknHH76SSDSx-1jCXwhYg0Rmj3R2N9hVYo0slWgfuwA8Y7-C2XRN0gcRS66c5rqt7eqyvV7LWTHM/s400/2.bmp" width="400" /></a></div><div style="font-family: Verdana,sans-serif;"><span style="font-size: small;"><br />
</span></div></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Permission to make digital or hard copies of all or part of this work for personal or classroom use is granted without fee provided that copies are not made or distributed for profit or commercial advantage and that copies bear this notice and the full citation on the first page. To copy otherwise, or republish, to post on servers or to redistribute to lists, requires prior specific permission and/or a fee</span></span>.</div><div style="text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;"> <br />
Where (Vip - Vin) is the differential input voltage, VDD and VSS are the power supply voltages, (C1/C2) . (C4/C5) defines the amplifier gain and the term [1/2 - (C7/C5)] corresponds to the DC level shift at the output. The pressure sensor can be modeled as a resistive Wheatstone bridge with a differential output signal ratiometric to (VDD-VSS). Also, the ADC voltage reference is ratiometric to (VDDVSS). Therefore the DC level shifting at DA's output is proportional to the power supplies as well (nominally 600mV when VDD = 3V and VSS = 0V). Both gain and offset capacitor array ratios can be adjusted by ± 25% around 16 and 0.2, respectively, during calibration process. Each DA stage compensates for op amp gain and op amp offset errors. Also, first stage has a high immunity to virtual ground (or analog ground) variations thanks to its fully differential architecture. The overall DA linearity is 9 bits (equivalent to the 10-bit ADC linearity). Due to its active calibration feature the Differential Amplifier gain accuracy has been set to 8 bits. However, noise floor in switches and capacitors is limited to 1/2 LSB within 10- bit resolution. In other words the DNL of the amplifying stage is 1/2 LSB at 10-bit resolution. Additional specifications of the circuit are: (a) power supply range from 2.1V to 3.6V; (b) input bandwidth of 100Hz; (c) DC input level at VDD = 3V: 1.5V ± 500mV; (d) sampling frequency of fclk = 125KHz; (e) temperature range from -40ºC to 125ºC; and (f) typical current consumption of 40uA.<br />
<b style="color: #93c47d;"><br />
3. CIRCUIT DESIGN</b><br />
<br />
The switched-capacitor amplifier shown in Fig. 2 implements the gain stage cell and is the fully-differential counterpart of the amplifier presented in [1]. It is based on the Correlated Double Sampling (CDS) technique widely used to minimize errors due to finite offset voltages, 1/f noise, and finite op amp gain [2]. The CDS technique does not require a reset of the output in each clock phase, which alleviates the slew-rate requirements for the op amp. Also, as the non-ideal op amp effects are reduced, a more relaxed op amp specification for low frequency inputs can be attained. The ground reference AGND comes from the analog ground generator and typically is 0.5*(VDD-VSS). The classical feedback reset switch is replaced by the elementary sample-and-hold branches consisting of capacitors C3 and their associated switches.</span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;"><br />
</span><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiSMNhRm1Jrgue8DCC1xlSY0Z30AxLHLQk6QWyrM4fY8N4cGWgDku-sOFj93KKO76TxOQA-8_3wpNN15ese4S5LnW6ovKPSYmIMMt9DLseEO8mFfG1YrWa_1LeIrumsZckOp1lqelYlQDE/s1600/3.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="338" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiSMNhRm1Jrgue8DCC1xlSY0Z30AxLHLQk6QWyrM4fY8N4cGWgDku-sOFj93KKO76TxOQA-8_3wpNN15ese4S5LnW6ovKPSYmIMMt9DLseEO8mFfG1YrWa_1LeIrumsZckOp1lqelYlQDE/s400/3.bmp" width="400" /></a></div><span style="font-family: Verdana, sans-serif; font-size: small;"><br />
During amplification phase (F2), sampling capacitors C1 discharge into C2 and the valid differential output is generated. This output is stored in C3. In the sampling phase (F1), capacitors C3 become the feedback capacitor while capacitors C1 sample the difference among the input voltages and the voltages at the opamp inputs (vp and vn nodes). At the same time, any offset voltage will be diferentially stored onto C2. In the next amplification phase, this offset voltage will be subtracted and cancelled. As the input signal bandwidth is much smaller than half the sampling frequency, i.e., the signal is significantly oversampled, Vop and Von do not vary much from one clock phase to the next. Thus, for a finite op amp gain (Av), the signal voltage at the inputs of the op amp is a slowly varying signal which is therefore nearly cancelled by the CDS switching of C1 and C2. This reduces the effect of finite op amp gain on the voltage gain of the stage. Detailed analysis of the fully-differential SC amplifier of Fig. 2 shows its DC gain is given by:</span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;"><br />
</span><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEis5bEgZV4IwKIDz9_UzaFveooOVmKDV-G3sizGb7xWNNli6glPY3yQci8uUiEja67ws32sCLRGyIqY8wuhsHnuKpVuoYF0n3VXzDXkF02BxgsX6JlaHB1Zik7J4X6vj0A-r3UCUXLS-ng/s1600/4.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="63" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEis5bEgZV4IwKIDz9_UzaFveooOVmKDV-G3sizGb7xWNNli6glPY3yQci8uUiEja67ws32sCLRGyIqY8wuhsHnuKpVuoYF0n3VXzDXkF02BxgsX6JlaHB1Zik7J4X6vj0A-r3UCUXLS-ng/s400/4.bmp" width="400" /></a></div><span style="font-family: Verdana, sans-serif; font-size: small;"> Eq. 2 shows that the voltage gain does not depend on capacitors C3 while the gain error is proportional to Av-2 rather than Av-1. This feature allows us to adopt a moderate-gain (~70dB) foldedcascode op amp without causing large errors in the amplifier gain. Besides reducing errors caused by op amp offset voltage and finite gain, the clock-feedthrough noise is also minimized by opening the switches connecting C3 to the op amp inputs (phase F1A) slightly before than closing the switches connecting C2 to analog ground (bottom plate sampling). Trimming capability is accomplished dividing each sampling capacitor in 3 sets (C1-1, C1-2 and C1-3) of unit capacitors (Cu) as long as C2 is also set to be equal to Cu. By default C1-1 = 12Cu and C1-2 = 4Cu define the sampling capacitor, so (C1/C2) = 16. By adding C1-3 = 4Cu to the sampling capacitor, the amplifier gain becomes 20 whereas taking off C1-2 from the default value, the gain is set to 12. The MiM capacitor size was initially estimated from maximum noise restriction but it provided a too small cap bound (1.45fF).<br />
<br />
Being the DC amplifier gain determined by the capacitor ratio C1/C2, a proper matching level is needed to achieve an overall linearity of 9 bits. Such matching level set a minimum capacitor size. From mistmatch data for MiM capacitors in our CMOS process, it was estimated the minimum capacitor size to obtain a mistmatch error of 0.0894% (equivalent to have an effective number of bits - ENOB - of 10.128 bits). So, for such a capacitor size, Cu was obtained. Additionally, to limit noise injection from the substrate, the plates of all the capacitors tied to the op amp inputs were maintained in the top metal mask. The switch sizes were calculated based on the settling time error constraint. To get an error less than 0.5LSB for 10 bits, operating at a clock frequency of half clock frequency and taking into account a sampling capacitor of 16Cu, the minimum switch resistor value obtained using hand calculations was 100KOhms.</span></div><div style="text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;"><br />
Then, it can be adopted devices with minimum geometries. Although, leakage imposes a channel length sligthtly higher than the minimum allowed. Fig. 3 illustrates the schematic of the op amp. It is a fullydiferential, folded-cascode, n-channel input transistors operational amplifier. One interesting feature about this opamp is its flexibility to be used either as a fully-differential or a single-ended amplifier. For single-ended applications, the inverted output terminal (OUTN) must be connected to the common-mode feedback input (CMC) which would normally be used by the common-mode feedback circuit to define the common-mode output voltage in fully-differential architectures. The use of low threshold voltage (Vth) transistors at the differential pair guarantees its operating voltage down to 1.7V. Typical electrical parameters for the op amp are 76dB open loop gain, 1.1MHz unit gain frequency with 69o phase margin, 11mA power consumption and output voltage swing ranging from VDD - 270mV to VSS + 230mV.</span><br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgqPmUQW1agjmvQGeZqmfX7IyUF6XBlzY1wePXE8-wUSXWfRF1E1yXwwtyWUD3NE8Sbs-XtPPU2pWjZe7DWYUDre62ganG86m7JgYSLSsVJBq_vodCzYbc7hbJWUeF0zuMC5DUtTGI_kS4/s1600/5.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="251" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgqPmUQW1agjmvQGeZqmfX7IyUF6XBlzY1wePXE8-wUSXWfRF1E1yXwwtyWUD3NE8Sbs-XtPPU2pWjZe7DWYUDre62ganG86m7JgYSLSsVJBq_vodCzYbc7hbJWUeF0zuMC5DUtTGI_kS4/s400/5.bmp" width="400" /></a></div><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg7yKv74_KG1mcnIU4SwWmJbH5d0UoCjrWZiPjYJerTMSwEIGPDZJBI46AWi6YqYIBI4OL1TV4W-pwGVb4seFcfBPBkxxkAgYDzBqjYkHfOzh0mzqJ3lusdnnNC8wyJvIOYq6oRx8H3rLc/s1600/6.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="262" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg7yKv74_KG1mcnIU4SwWmJbH5d0UoCjrWZiPjYJerTMSwEIGPDZJBI46AWi6YqYIBI4OL1TV4W-pwGVb4seFcfBPBkxxkAgYDzBqjYkHfOzh0mzqJ3lusdnnNC8wyJvIOYq6oRx8H3rLc/s400/6.bmp" width="400" /></a></div><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">The SC common-mode feedback (CMFB) circuit is shown in Fig. 4. It employs a switched-capacitor configuration with symmetric loading of the differential mode loop [3]. The symmetric loading is obtained doubling the circuit in Fig. 4 and exchanging the clock phases. This guarantees that both sampling and setting of the common-mode output are simultaneously performed at every clock phase. Therefore the op amp common-mode output settles much faster than (almost twice as fast as) using the traditional CMFB topology. To guarantee the CMFB circuit properly settles in PVT (process, voltage and temperature ranges), the Differential Amplifier starts working at half the clock frequency and, after 32 cycles (512ms), the clock is reduced to fclk/8 to minimize op amp settling time errors. After the common-mode feedback circuit stabilizes, a commonmode signal will appear at the inputs of the opamp. Note the common-mode signal is close to the analog ground plus the opamp offset voltage. However, that fact does not cause any harmful effects since the op amp common-mode rejection ratio is adequate (144dB typical). Further, parasitic capacitances at the op amp input terminals have not effect on the gain; the impact of other stray caps is diminished as long as they are well matched; careful layout addressed the demand of maintaining similar parasitic capacitance along all the differential paths. Fig. 5 is the schematic of the differential to single-ended stage. It is based on the same SC CDS architecture adopted for the fullydifferential amplifier stage but adapted to be a single-ended unity gain amplifier. Neglecting op amp finite gain and input offset errors, the transfer function of the second stage is given by:</span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;"><br />
</span><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjaaf0mWEys0ShbbhJKsdDNiE2L68pifOGY8kmAanttt14oApJUDqmPqWyZvM0M3NqJtPtjpmkdyhIoQP8IujUOoNm3UwzPy_iCxP3jKa1aQbZn5v_5Qn-OJ4VkJqSVtXQotBdYGr_004k/s1600/7.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="57" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjaaf0mWEys0ShbbhJKsdDNiE2L68pifOGY8kmAanttt14oApJUDqmPqWyZvM0M3NqJtPtjpmkdyhIoQP8IujUOoNm3UwzPy_iCxP3jKa1aQbZn5v_5Qn-OJ4VkJqSVtXQotBdYGr_004k/s400/7.bmp" width="400" /></a></div><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsWf0kyohKG-Z23qtcZXPo0pMA6W5_ibgL4BQw5G809UmrrFjS6HtvUB7nW8mcQ1HPkW5S-45mKMEsRt4yVJVcS2lMBhQaXzm3dyWmbBxD0daLehuCUCSbXNprjMPDn3EsnpYZIrM7-so/s1600/8.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjsWf0kyohKG-Z23qtcZXPo0pMA6W5_ibgL4BQw5G809UmrrFjS6HtvUB7nW8mcQ1HPkW5S-45mKMEsRt4yVJVcS2lMBhQaXzm3dyWmbBxD0daLehuCUCSbXNprjMPDn3EsnpYZIrM7-so/s400/8.bmp" width="356" /></a></div><span style="font-family: Verdana, sans-serif; font-size: small;"><br />
</span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">To allow the op amp to operate in a single-ended configuration, its inverted output was tied to the common-mode feedback terminal to self-bias the NMOS current sources. For unity gain both C4 and C5 equal 2Cu. The offset is introduced through C7 capacitor array and its respective switches. The offset capacitor size is adjusted to be one tenth of Cu. Note the offset trimming switches are connected either to VDD or VSS. The offset trimming is attained by properly choosing a specific charge transfer ratio between the offset capacitor array (C7) and the feedback capacitor (C5). By default, the offset trimming capacitor is set to 6Cu/10, so it gives an offset voltage at the output of 0.20*VDD. By adding Cu/10 to the offset trimming capacitor, the offset voltage will be 0.15*VDD whereas subtracting Cu/10 to that the offset voltage becomes 0.25*VDD. With such arrangement the output offset voltage of the Differential Amplifier can be trimmed by ±25% around 0.20*VDD. Additionally, it was necessary to design an analog ground generator, a current source for biasing all the circuits, and a clock generator that provides all non-overlapping clock phases necessary to drive the analog switches. As proper circuit operation derives from 2.5V control logic, digital level shifters were included as well.<br />
<br />
<b style="color: #93c47d;">4. EXPERIMENTAL RESULTS</b><br />
<br />
The Differential Amplifier has been integrated into a SoC realized in a standard 4-metal single-poly 0.25um CMOS process with metal-metal capacitors. Fig. 6 shows a microphotograph of the module with its main sub-blocks outlined. Clkgen stands for nonoverlapping multi-phase clock generator and Iref for current source. The module occupies a silicon area of 0.115 mm2 (480um x 240um) mostly due to large high-linearity capacitor arrays for achieving high accuracy on capacitor ratios. Silicon evaluation proved the module to be perfectly functional with very good overall performance such as: high linearity, high repeatability, low temperature sensitivity, high power supply rejection ratio and high input common-mode rejection ratio.</span><br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh2yFzCbFrUhGHNTbCewCTtyEr-PThilTUgyBzQIg98yxrytpi9WhauDdBIXuYDwVzrPaQtDgvTQPpQaHnVgTIaVHxzTGTTygXVRkx1Y0kK3XQ8ZVlIUrzZCl8GxjQ-RbhBAlk43ShL78Q/s1600/9.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="200" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh2yFzCbFrUhGHNTbCewCTtyEr-PThilTUgyBzQIg98yxrytpi9WhauDdBIXuYDwVzrPaQtDgvTQPpQaHnVgTIaVHxzTGTTygXVRkx1Y0kK3XQ8ZVlIUrzZCl8GxjQ-RbhBAlk43ShL78Q/s320/9.bmp" width="320" /></a></div><span style="font-family: Verdana, sans-serif; font-size: small;"><br />
As the DA was designed to have its single-ended output sampled by an ADC, there is no access to its internal nodes during normal operation. In a SoC special operating mode, however, some critical nodes are routed to external pins so they can be monitored through the oscilloscope. This feature is achieved at the cost of higher noise injected by the chip into the module. Also the extra routing, bonding and probing in this operating mode add large capacitive loads into its switched-capacitor architecture demanding a slower switching clock and slightly degrading its performance due to leaky phase-to-phase charge transfer. Fig. 7 illustrates the DA measuring cycle in the SoC special operating mode for zero differential input voltage at 3V power supply. Horizontal and vertical scales are 400us and 0.5V respectively (except ADC trigger signal which is 2V vertical). 1st stage outputs remain at 1.5V while 2nd stage sustains a DC level as determined by the offset selection circuitry. At 80mV differential input, 1st and 2nd stages operate according to Fig. 8. It is apparent that a fast clocking rate is applied at the beginning. Although this short phase time does not allow for a proper settling time, all DA capacitors are rapidly charged. Once all nodes in the switched-capacitor architecture approach their steady state, the clock rate is reduced and subsequent phase cycles follow to precisely define its output. Since the voltages in a switchedcapacitor circuit reach steady state at the end of each phase, the clock is halted at the end of phase 2 (after a defined number of cycles) prior to triggering the ADC with a positive transition in the ADC trigger signal.</span><br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgs-TCIxOaQVBL5CgcGEiFn5-UfQAZimkEkSVJm9KkmBLypZW4EusaBm2tFGLlYxT5Lx30oYARzoso4tSrskOglghBbJEBVJjdO_I6qUVTA5RI5yEmN5Y156rTlE2k4LysdcTTxYxrAWOY/s1600/10.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="152" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgs-TCIxOaQVBL5CgcGEiFn5-UfQAZimkEkSVJm9KkmBLypZW4EusaBm2tFGLlYxT5Lx30oYARzoso4tSrskOglghBbJEBVJjdO_I6qUVTA5RI5yEmN5Y156rTlE2k4LysdcTTxYxrAWOY/s400/10.bmp" width="400" /></a></div><br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjirdjust6Mt3NvchNQ4DNaJjml8506CxH7HnD9ku6O3v_g7rlji_mcwxBj09cFZ8a9QNP3RmylcsLSSqRVe9E0amAh0OCZ2wM7MlEhooiRy_HPCaHak0EmaSP0W0HrftpYl-6h6nhaiAI/s1600/11.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="152" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjirdjust6Mt3NvchNQ4DNaJjml8506CxH7HnD9ku6O3v_g7rlji_mcwxBj09cFZ8a9QNP3RmylcsLSSqRVe9E0amAh0OCZ2wM7MlEhooiRy_HPCaHak0EmaSP0W0HrftpYl-6h6nhaiAI/s400/11.bmp" width="400" /></a></div><span style="font-family: Verdana, sans-serif; font-size: small;"><br />
<br />
<b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">5. CONCLUSION</span></b><br />
<br />
A low-power differential switched-capacitor amplifier for processing a fully-differential input signal coming from a pressure sensor interface has been presented. A SoC device integrating the amplifier has been realized in a 0.25um CMOS technology and silicon results proved the amplifier to be fully operational down to1.8V with 40uA typical supply current. Its very good overall performance derives from its high linearity, high repeatability, high power supply rejection ratio and high common-mode input rejection ratio.<br />
<br />
Hernández Caballero Indiana<br />
Asignatura: CAF<br />
Fuente:<a href="http://www.freescale.com/files/technology_publications/doc/Papers/Eintell5342.pdf">http://www.freescale.com/files/technology_publications/doc/Papers/Eintell5342.pdf</a></span></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-6177282538638165582010-07-25T23:22:00.002-04:302010-07-27T16:49:46.537-04:30VERY LOW-VOLTAGE FULLY DIFFERENTIAL AMPLIFIER FOR SWITCHED-CAPACITOR APPLICATIONS<h3 class="post-title entry-title"><a href="http://indianamaithe.blogspot.com/2010/07/very-low-voltage-fully-differential.html"></a> </h3><div class="post-header"></div><div style="text-align: justify;"><b style="color: #93c47d;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">ABSTRACT</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">A fully differential opamp suitable for very-low voltage switched-capacitor circuits in standard CMOS technologies is introduced. The proposed two stage opamp needs a simple low voltage CMFB switched-capacitor circuit only for the second stage. Due to the reduced supply voltage, the CMFB circuit is implemented using bootstrapped switches. Minor modifications allow to use chopper stabilization for flicker noise reduction. Two different compensation schemes are discussed and compared using an example for 1V operation of the amplifier.</span></span><br />
<b style="color: #93c47d;"><br style="font-family: Verdana,sans-serif;" /><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">1. INTRODUCTION</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The increasing interest in low-voltage, low-power integrated circuits has lead to modifying the existing circuit techniques in order to be able to work correctly under these new constraints. In switched-capacitor circuits, reducing the supply voltage increases drastically the switch resistance.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">One technique to overcome this problem is clock voltage multiplication. This however is not power efficient and not compatible with very advanced low-voltage CMOS processes where gate oxide breakdown becomes an issue.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Some designs use low threshold transistors for the switches. Obviously, a special process is required. Alternatively, the switched-opamp technique (SO) [1] has been proposed to get around this problem. However, the circuit becomes more complicated and loses some of the speed. This results in relatively poor performance of the switched-opamp circuits.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">In [2] a bootstrapped switch is introduced that allows rail-to-rail operation of a single n-switch in a standard CMOS process. Together with using different common mode (CM) voltages at the input and the output of the opamp, this leads to possible rail-to-rail operation of very low-voltage switched-capacitor circuits with the least modifications introduced to existing designs and in the same time enhancing the linearity performance due to the constant drive of the bootstrapped switches [2]. This shift of the CM voltage could be achieved either by injecting a fixed amount of charge at the opamp input at each clock cycle [2], or by using different reference voltages at the input and output of the differential switched-capacitor integrator as shown in Fig. 1. Both the input signal and the amplifier</span></span> <span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">output has a CM voltage equal to Vcm-out which is usually chosen near the mid-supply range in order to maximize signal excursions. Bootstrapped switches are thus used to switch signals around Vcm-out. On the other hand, the amplifierinput CM voltage is at Vcm-in which is near V SS such that single n-switches are sufficient.</span></span></div><div style="text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjJWVDqHACC7DgGR8Gg1BjxZEuoHIa7fdtDBSqVyU5e5m1wVQM_4EBlczzG4XyTGOxFIEDRjkBjM8Nyq3QVO90yik0NW3FtY-yquufdxDMWLu_FEE1VyJNCSCg7J_d8Sx89y5OC6bq_7XM/s1600/1.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="283" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjJWVDqHACC7DgGR8Gg1BjxZEuoHIa7fdtDBSqVyU5e5m1wVQM_4EBlczzG4XyTGOxFIEDRjkBjM8Nyq3QVO90yik0NW3FtY-yquufdxDMWLu_FEE1VyJNCSCg7J_d8Sx89y5OC6bq_7XM/s400/1.bmp" width="400" /></a></div><div style="text-align: justify;"><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Since reduced supply voltage forces current consumption to increase [3], the amplifier topology plays a critical role in low-voltage, low-power switched-capacitor design. Additional circuitry for common-mode operation must also be considered in the same time so as not to degrade the overall amplifier performance.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">In [4] a 1V two-stage amplifier is designed for the SO technique.</span></span> <span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">It is based on a p-type folded-cascode two stage Miller-compensated structure. An additional common-mode amplifier, also performing the necessary signal inversion, is used for the CMFB. The overall opamp operates at a minimum supply voltage of VGS +VDSsat, but speed and power consumption are both limited by the additional CMFB amplifier.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">In [5], the same opamp is used but with the CMFB in the first stage implemented using a cross-coupled transistor stage. CMFB in the second stage is achieved using a simple passive circuit suitable only for SO circuits. The minimum supply voltage needed is however increased by one VDSsat.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">This paper introduces further modifications to the above cross-coupled connection so as to reduce the minimum supply voltage. Bootstrapped switches allow a simple switchedcapacitor CMFB circuit to be used. Two compensation schemes are considered and compared with respect to the amplifier performance. As the signal level is reduced for reduced supply voltages, the noise level becomes more critical. Special noise reduction techniques are discussed for the modified architecture.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The paper is organized as follows: Section 2 introduces the modified opamp structure. In section 3, simulation results are shown comparing the two possible compensation schemes. Finally, conclusions are summarized in section 4.</span></span><br />
<b style="color: #93c47d;"><br style="font-family: Verdana,sans-serif;" /><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">2. PROPOSED OPAMP</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">For the differential opamp shown in Fig. 1, the low supply voltage prevents the use of stacked transistors so that a twostage amplifier is usually needed to achieve the required dc gain.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">An input PMOS differential pair allows the use of V SS as the opamp CM input voltage Vcm-in.</span></span></div><div style="text-align: justify;"><b style="color: #93c47d;"><br style="font-family: Verdana,sans-serif;" /><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">2.1. Common-Mode Feedback</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Due to the differential structure, the common mode output voltage of both stages needs to be regulated using CMFB. Biasing of class-A amplifiers is typically accomplished with a CMFB circuit that senses the output CM voltage in order to control the tail current source via a current mirror. However, owing to stability considerations, the gain and bandwidth of the CMFB loop are limited to at most those of the differential mode signal path. Moreover, power consumption is increased due to the added CMFB circuitry.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Fig. 2 shows the proposed amplifier structure. The NMOS cascode current source has been split into two equally-sized, cross-coupled devices (M51, M52 and M61,M62) with their gates connected to the two outputs of the first stage (nodes n3 and n4). This negative feedback connection causes the differential signal at the output of the first stage (nodes n3 and n4) to see a high load impedance given by the reciprocal of </span></span></div><div style="text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi71ItlZvfxSlZ08DZdDN9u3nN8MlCYTi21FbBaFFAGtASMN0m6wVadaX1pheqPm3l46nXy7q6gxhNQ8F4y1EuMR9HfRxP6iNK9cYyFBOrDLZhdpTptDIxLKHE2EGvMgXDvZfIz2qQfQuM/s1600/2.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="80" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi71ItlZvfxSlZ08DZdDN9u3nN8MlCYTi21FbBaFFAGtASMN0m6wVadaX1pheqPm3l46nXy7q6gxhNQ8F4y1EuMR9HfRxP6iNK9cYyFBOrDLZhdpTptDIxLKHE2EGvMgXDvZfIz2qQfQuM/s400/2.bmp" width="400" /></a></div><div style="text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi3yD6_MUnRshbf3WOOfiIoB1yD3XqML8k7PmKCKhcbXfyncbwMAGOyUmjxMF7yuLU0T-G2hBl6FoWuVcvbU2mlNmTN3jCVzcqMIASXmVuaJibnYHSGhwi2rp1wvyyZ7guUfg4VIbYaMrU/s1600/3.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="293" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi3yD6_MUnRshbf3WOOfiIoB1yD3XqML8k7PmKCKhcbXfyncbwMAGOyUmjxMF7yuLU0T-G2hBl6FoWuVcvbU2mlNmTN3jCVzcqMIASXmVuaJibnYHSGhwi2rp1wvyyZ7guUfg4VIbYaMrU/s400/3.bmp" width="400" /></a></div><div style="text-align: justify;"></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The conductance gm51 seen at the gate of transistors M51 and M61 is thus canceled by the opposite action of the parallel transistors M52 and M62 respectively. Proper matching of these transistors, together with other terms in equation (1) prevent the output resistance from going negative. The total conductance gdsout1 is thus limited by gds8.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">On the other hand, for the common mode signal, the output conductance is also given by equation (1) but with the negative term turned positive. The total conductance gdsout1 in this case is limited by gm51 + gm52. This impedance is a low one and thus the first stage does not require an additional CMFB circuit. In fact the cross-coupled devices act like a built-in CMFB circuit that senses the output of the first stage and regulates its common mode voltage. It also allows a minimum supply voltage of VGS + VDSsat.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The second stage is composed of the NMOS common source amplifier M11(M13) with active load M10(M12). A simple passive switched-capacitor CMFB circuit (shown in Fig. 1) can be used in this case. The dc voltage across C1 is determined by capacitor C2 which is switched between being in parallel with C1 and Vcm-out-Vb, where Vb is the desired biasing voltage for the current source ptransistors M10 and M12. Since the potential Vb is close to V SS, n-transistors can be used to switch it. However, bootstrapped switches must be used in the CMFB circuit for those switches that have to switch the Vcm-out potential.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">These bootstrapped switches can be shared with the sampling network connecting the integrator output to subsequent stages as shown in Fig. 1.</span></span><br />
<br />
<b style="color: #93c47d;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">2.2. Opamp Compensation</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Two possible compensation schemes are possible for this two-stage opamp structure: The first one is the standard Miller compensation scheme which consists of connecting the compensation capacitor CC in series with a compensation resistance RC between the output nodes and the output of the first stage (nodes n3 and n4). Analysis of the amplifier shows that the transfer function has five poles and two zeros that can be placed in the half-left plane. A sort of pole-zero cancellation is also possible by properly choosing the value of RC. This further enhances the phase margin.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The second compensation scheme is shown in Fig. 2. This is done by connecting the compensation capacitor CC to the source of the cascode devices (nodes n1 and n2) [6]. These low impedance points decouple the gate of the output stage amplifier (transistors M11 and M13) from the compensation capacitor. This technique offers a much improved highfrequency power-supply rejection ratio (PSRR) and moves the right-half plane zero resulting from Miller compensation into high frequencies. It can be shown [6] that this type of compensation results in two complex poles besides the dominant one. It is thus quite possible to obtain a design with adequate phase margin, which suffers from insufficient gain margin due to gain peaking beyond the unitygain bandwidth, caused by a high pole quality factor Qp.</span></span> <span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">This pole quality factor Qp is given by [6] </span></span></div><div style="text-align: justify;"></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi4T3HPVzVRqd88o2tooH_vuUTFy-JVZ8myEfpLiu7rU5Q6h52R_qYP9JTyq1uI63wZCKoR-piLFM8X0rrikmWSVTqRPVZ3cBdidtCGmL2UTJv25jDzSWZ24_CXN5d5Q5Cc_f8e-pF8Jos/s1600/4.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="77" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi4T3HPVzVRqd88o2tooH_vuUTFy-JVZ8myEfpLiu7rU5Q6h52R_qYP9JTyq1uI63wZCKoR-piLFM8X0rrikmWSVTqRPVZ3cBdidtCGmL2UTJv25jDzSWZ24_CXN5d5Q5Cc_f8e-pF8Jos/s400/4.bmp" width="400" /></a></div><div style="text-align: justify;"></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">It can be kept low by making the transconductances of the cascode transistor M3(M4) large compared to the output driver M11(M13). In addition a moderate value of CC is required.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Both schemes ensure stability. Low-Qp considerations for the second one usually impose more constraints on the design of the amplifier. High cascode transconductance implies either lower VGS-Vth or higher current. Lower VG-Vth leads to higher parasitic capacitance which will reduce the amplifier bandwidth. This implies an optimum VGS-Vth value. Higher cascode current implies larger power consumption and higher input referred thermal noise. In addition, the value of the compensation capacitance CC in the second case is limited by the required Qp. Since the aliased input referred in-band white noise in switched-capacitor circuits is inversely proportional to the value of the compensation capacitor of the amplifier, this restricts the white noise performance optimization.</span></span><br />
<br />
<b style="color: #93c47d;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">2.3. Noise Reduction</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">For low-noise input front-ends, the input amplifier noise optimization is an important step in the overall system design. Thermal noise can be reduced using higher input current in the input differential pair. While flicker noise can be reduced using larger areas for the transistors contributing to the flicker noise (namely M1, M2, M5, M6, M8 and M9). This causes higher parasitic capacitance on the internal</span></span> <span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">nodes and thus increases the amplifier power consumpch2 tion. To overcome this, techniques such as chopper stabilization [7] can be used. For the proposed amplifier, the input is chopped using four input n-switches as shown in Fig. 1. On the other hand, the output of the first stage is chopped as shown in Fig. 3 using only two additional cascade transistors M32 and M42 in parallel with the existing ones but with their sources connected to nodes n2 and n1 respectively. The gates of both cascodes are then driven by two overlapping chopper clocks (Øch1 and Øch2) at half the sampling frequency. The two chopper clocks must overlap to avoid the simultaneous cutoff of both cascodes in parallel in the same time which would increase the settling time of the opamp. Using the supply as the gate bias of the cascade transistors eliminates the need of an additional biasing voltage. This arrangement reduces the 1=f noise for all transistors but M8 and M9 where a larger transistor length must be used.</span></span></div><div style="text-align: justify;"><br style="font-family: Verdana,sans-serif;" /></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjt3THWtpt8iWVU8rjNIhnVzRT9hbrPywya-GdDhZZvMQVG9Ucez_Xgl7GZBAMYAPYduHZyRO82G5SIcjHMOan6PHelw_pp2Cwy42R829JxQXB-U9KxnMOYU1Jh1Ri4cPR1GzPT4R7UFbo/s1600/5.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="297" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjt3THWtpt8iWVU8rjNIhnVzRT9hbrPywya-GdDhZZvMQVG9Ucez_Xgl7GZBAMYAPYduHZyRO82G5SIcjHMOan6PHelw_pp2Cwy42R829JxQXB-U9KxnMOYU1Jh1Ri4cPR1GzPT4R7UFbo/s400/5.bmp" width="400" /></a></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">It should be noted that the input chopper switches, shown in Fig. 1, create an additional pole together with the input capacitance of the opamp. This pole must be considered during the amplifier design.</span></span><br />
<br />
<b style="color: #93c47d;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">3. RESULTS</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">As an example of the proposed architecture, table 1 shows the simulated results of two sized netlists. The first using the cascode compensation scheme, and the second (shown between brackets for different values) using the Miller scheme with a nulling resistor to compensate for the right half-plane zero. Both circuits are sized for the same supply voltage, unity-gain frequency, phase margin, slew rate, and output voltage range in order to be able to compare them. A 0.35_ technology is used with a p- and n-transistor thresholds of 0.63 V and 0.6 V respectively. It is to be noted that for the CMFB network shown in Fig. 1, the capacitor C1 loads the amplifier output. At the same time, it is connected to the Vcmfb input of the amplifier which has an input capacitance equal to double the gate ca pacitance of M10. A capacitor divider thus exists and some gain of the CMFB network is lost. To overcome this problem, C1 is chosen to be five times the size of the input capacitance at Vcmfb. During sizing this capacitance is limited to 20% of the load capacitance.</span></span></div><div style="text-align: justify;"><br style="font-family: Verdana,sans-serif;" /></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgJTpMxwZryb7A2MW1BAv3MRdZVK5UcdAKgELpI45cWk9OfmPgRpBifdCHxnjrcQ-TCdbgTJrcoIklm6ripReH3XsPBevQHYqiBT8IFeWUOAic2ABlo66ZmrORT0SmG3At_l9aLw4TC0Zg/s1600/6.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="355" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgJTpMxwZryb7A2MW1BAv3MRdZVK5UcdAKgELpI45cWk9OfmPgRpBifdCHxnjrcQ-TCdbgTJrcoIklm6ripReH3XsPBevQHYqiBT8IFeWUOAic2ABlo66ZmrORT0SmG3At_l9aLw4TC0Zg/s400/6.bmp" width="400" /></a></div><div style="text-align: justify;"></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">For the cascode compensation scheme, a lower compensation capacitance value could be used, this reduces the overall power consumption. However, due to low-Qp considerations it is more difficult to obtain a satisfactory gain. The high-frequency PSRR is also better for cascode compensation. Careful layout can further enhance the PSRR performance for both cases as supply noise is considered as a CM signal and is cancelled at the differential output of the amplifier.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Additional transistors for chopper stabilization are taken into account during sizing. Flicker noise can thus be neglected. Fig. 4 shows the simulated open-loop gain for both cases, gain peaking can be easily identified for the cascade compensation case. Special care has been taken during sizing such that the complex pole quality factor Qp does not exceed unity.</span></span></div><div style="text-align: justify;"><br style="font-family: Verdana,sans-serif;" /></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjN98hXb8OuXlapMXQ_KmY60Y577ZmgIU0Bq58g4xCvkLYkA0JS6oh5LwyAsspLIvdyBe5tzWlGskzOovIdwQI_Xc9bpcsbAw9z1e7nrQrkVCzKBeNwqsEllUQqeFWZWOfoxAM3IbNsFI8/s1600/7.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjN98hXb8OuXlapMXQ_KmY60Y577ZmgIU0Bq58g4xCvkLYkA0JS6oh5LwyAsspLIvdyBe5tzWlGskzOovIdwQI_Xc9bpcsbAw9z1e7nrQrkVCzKBeNwqsEllUQqeFWZWOfoxAM3IbNsFI8/s400/7.bmp" width="366" /></a></div><div style="text-align: justify;"><b style="color: #93c47d;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">4. CONCLUSIONS</span></span></b><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The proposed fully differential opamp allows very low supply voltage operation and minimizes the additional CMFB circuitry thus saving the overall power. Conventional Miller and cascode compensation schemes are compared using a design example. Minor modifications allow the chopper-stabilization technique to be used for noise reduction. Combined with the switch bootstrapping technique, the proposed architecture permits robust very-low voltage switched-capacitor circuits to be constructed in standard CMOS technologies using common design techniques.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Hernández Caballero Indiana</span></span><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Asignatura: CAF</span></span><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Fuente: <a href="http://citeseerx.ist.psu.edu/">http://citeseerx.ist.psu.edu</a></span></span></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-55965665908317003882010-07-25T23:21:00.002-04:302010-07-27T16:49:22.431-04:30DISEÑO DE AMPLIFICADORES DIFERENCIALES DE BAJO RUIDO PARA ANTENAS UWB EN LA BANDA BAJA DEL PROYECTO SKA<div class="post-header"></div><div class="post-body entry-content"><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_filelist.xml" rel="File-List"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_themedata.thmx" rel="themeData"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_colorschememapping.xml" rel="colorSchemeMapping"></link> <style>
<!-- /* Font Definitions */ @font-face {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4; mso-font-charset:0; mso-generic-font-family:roman; mso-font-pitch:variable; mso-font-signature:-1610611985 1107304683 0 0 159 0;} @font-face {font-family:Calibri; panose-1:2 15 5 2 2 2 4 3 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:-1610611985 1073750139 0 0 159 0;} @font-face {font-family:"BIACNE+TimesNewRoman\,Bold"; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-alt:"Times New Roman"; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 0 0 0 1 0;} @font-face {font-family:Verdana; panose-1:2 11 6 4 3 5 4 4 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:536871559 0 0 0 415 0;} @font-face {font-family:TimesNewRoman; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 0 0 0 1 0;} @font-face {font-family:TimesNewRomanPSMT; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:131 0 0 0 9 0;} @font-face {font-family:TimesNewRomanPS-ItalicMT; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:131 0 0 0 9 0;} @font-face {font-family:SymbolMT; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:auto; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 0 0 0 1 0;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {mso-style-unhide:no; mso-style-qformat:yes; mso-style-parent:""; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:0cm; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} a:link, span.MsoHyperlink {mso-style-priority:99; color:blue; mso-themecolor:hyperlink; text-decoration:underline; text-underline:single;} a:visited, span.MsoHyperlinkFollowed {mso-style-noshow:yes; mso-style-priority:99; color:purple; mso-themecolor:followedhyperlink; text-decoration:underline; text-underline:single;} p.MsoListParagraph, li.MsoListParagraph, div.MsoListParagraph {mso-style-priority:34; mso-style-unhide:no; mso-style-qformat:yes; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:36.0pt; mso-add-space:auto; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} p.MsoListParagraphCxSpFirst, li.MsoListParagraphCxSpFirst, div.MsoListParagraphCxSpFirst {mso-style-priority:34; mso-style-unhide:no; mso-style-qformat:yes; mso-style-type:export-only; margin-top:0cm; margin-right:0cm; margin-bottom:0cm; margin-left:36.0pt; margin-bottom:.0001pt; mso-add-space:auto; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} p.MsoListParagraphCxSpMiddle, li.MsoListParagraphCxSpMiddle, div.MsoListParagraphCxSpMiddle {mso-style-priority:34; mso-style-unhide:no; mso-style-qformat:yes; mso-style-type:export-only; margin-top:0cm; margin-right:0cm; margin-bottom:0cm; margin-left:36.0pt; margin-bottom:.0001pt; mso-add-space:auto; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} p.MsoListParagraphCxSpLast, li.MsoListParagraphCxSpLast, div.MsoListParagraphCxSpLast {mso-style-priority:34; mso-style-unhide:no; mso-style-qformat:yes; mso-style-type:export-only; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:36.0pt; mso-add-space:auto; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} p.Default, li.Default, div.Default {mso-style-name:Default; mso-style-unhide:no; mso-style-parent:""; margin:0cm; margin-bottom:.0001pt; mso-pagination:widow-orphan; mso-layout-grid-align:none; text-autospace:none; font-size:12.0pt; font-family:"BIACNE+TimesNewRoman,Bold","serif"; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-bidi-font-family:"BIACNE+TimesNewRoman\,Bold"; color:black; mso-fareast-language:EN-US;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoPapDefault {mso-style-type:export-only; margin-bottom:10.0pt; line-height:115%;} @page Section1 {size:612.0pt 792.0pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} /* List Definitions */ @list l0 {mso-list-id:207138; mso-list-type:hybrid; mso-list-template-ids:299670746 201981973 201981977 201981979 201981967 201981977 201981979 201981967 201981977 201981979;} @list l0:level1 {mso-level-number-format:alpha-upper; mso-level-tab-stop:none; mso-level-number-position:left; text-indent:-18.0pt;} @list l1 {mso-list-id:307326493; mso-list-template-ids:122046186;} @list l1:level1 {mso-level-number-format:roman-upper; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:54.0pt; text-indent:-36.0pt;} @list l1:level2 {mso-level-legal-format:yes; mso-level-text:"%1\.%2\."; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:54.0pt; text-indent:-36.0pt;} @list l1:level3 {mso-level-legal-format:yes; mso-level-text:"%1\.%2\.%3\."; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:72.0pt; text-indent:-54.0pt;} @list l1:level4 {mso-level-legal-format:yes; mso-level-text:"%1\.%2\.%3\.%4\."; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:90.0pt; text-indent:-72.0pt;} @list l1:level5 {mso-level-legal-format:yes; mso-level-text:"%1\.%2\.%3\.%4\.%5\."; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:108.0pt; text-indent:-90.0pt;} @list l1:level6 {mso-level-legal-format:yes; mso-level-text:"%1\.%2\.%3\.%4\.%5\.%6\."; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:108.0pt; text-indent:-90.0pt;} @list l1:level7 {mso-level-legal-format:yes; mso-level-text:"%1\.%2\.%3\.%4\.%5\.%6\.%7\."; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:126.0pt; text-indent:-108.0pt;} @list l1:level8 {mso-level-legal-format:yes; mso-level-text:"%1\.%2\.%3\.%4\.%5\.%6\.%7\.%8\."; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:144.0pt; text-indent:-126.0pt;} @list l1:level9 {mso-level-legal-format:yes; mso-level-text:"%1\.%2\.%3\.%4\.%5\.%6\.%7\.%8\.%9\."; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:162.0pt; text-indent:-144.0pt;} @list l2 {mso-list-id:1597711268; mso-list-type:hybrid; mso-list-template-ids:-879076552 201981973 201981977 201981979 201981967 201981977 201981979 201981967 201981977 201981979;} @list l2:level1 {mso-level-number-format:alpha-upper; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:53.4pt; text-indent:-18.0pt;} ol {margin-bottom:0cm;} ul {margin-bottom:0cm;} -->
</style> <br />
<div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="color: black; font-family: Verdana, sans-serif; font-size: 12pt;"></span><span style="font-family: Verdana, sans-serif; font-size: small;">Abstract- Differential amplifiers can be an appropriate solution in the implementation of radio astronomy receivers, due to their efficient interference and harmonic isolation. In this paper, two different topologies are presented. The first one consists of two single ended amplifiers in a balanced topology. The second one is formed by cascading two simple differential stages. Both circuits operate in the 300MHz to 1GHz bandwidth. Firstly, gain and noise characterizations of each amplifier have been done. Lastly, noise analysis of the whole reception system, formed by the antenna and the differential amplifiers, is presented. </span></div><div style="text-align: justify;"><br />
<b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;">I. INTRODUCCIÓN </span></b> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">El proyecto SKA (Square Kilometer Array) es un esfuerzo de la comunidad internacional para investigar y desarrollar las tecnologías necesarias para construir un nuevo radiotelescopio en una extensión de un kilómetro cuadrado de área [1]. Este instrumento va a ser mucho más sensible que los radiotelescopios actuales, y va a funcionar en un ancho de banda comprendido entre los 100MHz y los 25GHz. </span> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Actualmente se están realizando gran cantidad de trabajos de investigación en este ámbito en todo el mundo. Una de estas tareas es el diseño de amplificadores de bajo ruido que funcionen en la banda de frecuencia entre 100MHz y 1GHz. El principal problema con los sistemas de radioastronomía que funcionan a esas frecuencias es el alto nivel de ruido atmosférico que reciben las antenas de banda ancha y no muy directivas. </span> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">El uso de antenas diferenciales (Vivaldy, Bunny Ear) para cubrir la banda baja del proyecto SKA hace que se planteen dos posibilidades en el diseño de los amplificadores de bajo ruido del receptor. Una primera aproximación puede consistir en conectar un balun a los puertos de la antena, y a continuación utilizar un amplificador de bajo ruido convencional single-ended. La otra solución no requiere el uso de baluns pasivos, que van a introducir pérdidas, sino que utiliza amplificadores diferenciales a modo de balun activo. El uso de dispositivos electrónicos diferenciales es bastante común en sistemas de baja frecuencia, pero su uso para frecuencias de microondas no está tan extendido. Sin embargo, para el caso de amplificadores de microondas de bajo ruido, el uso de una topología diferencial reduciría sustancialmente la cantidad de ruido acoplado en modo común (por ejemplo el introducido por las alimentaciones del amplificador). Por otro lado, hay problemas inherentes añadidos al trabajar con parámetros S diferenciales en vez de con los tradicionales. </span> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">En esta línea se han propuesto algunas soluciones, sobre todo basadas en tecnología MMIC [2] [3]. En este trabajo se presentan dos diseños alternativos basados en elementos concentrados y realizados en tecnología microstrip. </span> <br />
<br />
<span style="color: #93c47d; font-family: Verdana, sans-serif; font-size: small;"><b>II. AMPLIFICADORES DIFERENCIALES DE MICROONDAS</b> </span> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Las aplicaciones de baja frecuencia han venido utilizando circuitos balanceados durante años para reducir las interferencias y eliminar las líneas de referencia a masa. Hay muchas ventajas en el uso de de circuitos diferenciales en vez de los dispositivos single-ended. Estas propiedades no han pasado desapercibidas a los investigadores y diseñadores de circuitos, lo que ha provocado un gran incremento en su uso para aplicaciones de alta frecuencia y de microondas. Las principales ventajas que introducen son: </span> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">* Aislamiento frente a interferencias externas. </span> <br />
<span style="font-family: Verdana, sans-serif; font-size: small;">* Aumento del rango dinámico. </span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">* Reducción de la distorsión de los armónicos pares. </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Por otro lado, hay algunas desventajas inherentes en el uso de estos circuitos diferenciales en sistemas de microondas, y que hay que tener en cuenta en nuestro diseño: </span> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">* Se duplica el número de componentes. </span> <br />
<span style="font-family: Verdana, sans-serif; font-size: small;">* Se aumenta el tamaño necesario. </span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">* Mayor consumo de potencia. </span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">* Son más difíciles de diseñar y de caracterizar. </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Mediante el uso de los parámetros S en modo mixto [4], los cuales permiten extender los parámetros S convencionales de dos puertos a un dispositivo diferencial de cuatro puertos, la última desventaja puede ser mitigada en gran medida. Además, el desarrollo de los analizadores de redes vectoriales en modo puro (PMVNA – Pure Mode Vector Network Anayzer) [5], [6], que permiten medir directamente estos parámetros S en modo mixto, pueden ser un punto clave que facilite el diseño y caracterización de este tipo de dispositivos. Por lo tanto, los circuitos diferenciales pueden convertirse en una solución práctica en muchos sistemas de microondas. </span> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Dos topologías típicas de amplificadores diferenciales son las que se muestran en la Fig. 1. La primera consiste en dos etapas amplificadoras single-ended independientes e idénticas, con entrada y salida tomadas de forma diferencial (topología balanceada). La segunda usa dos transistores con fuente de corriente común (topología diferencial clásica). La principal diferencia entre ambas es que la segunda introduce un parámetro de calidad que se conoce como rechazo en modo común (CMRR – Common Mode Rejection Ratio), que relaciona la ganancia en modo diferencial Sdd21 y la ganancia en modo común Scc21 como </span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;"> </span> </div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjTUyDhqmLDIn4T6bjjskPX9nYkFH4t6JdfVzzpIprQ-BKq8S82Q74sTafqrfmqAAhB7lKfXRDTrNajdp5LZOWYlA4ijEjyZiaXfyy8ZVuwpD7jz2dAOj6GaZWTTfHjoplxA0K8a4qCCaY/s1600/1.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjTUyDhqmLDIn4T6bjjskPX9nYkFH4t6JdfVzzpIprQ-BKq8S82Q74sTafqrfmqAAhB7lKfXRDTrNajdp5LZOWYlA4ijEjyZiaXfyy8ZVuwpD7jz2dAOj6GaZWTTfHjoplxA0K8a4qCCaY/s320/1.bmp" /></a></div><div style="text-align: justify;"><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">La topología balanceada no presenta esta propiedad, ya que amplifica las señales que se introducen en modo común por los puertos de entrada y que se recuperan también en modo común en los puertos de salida. Por el contrario, el esquema diferencial anula este tipo de señales perfectamente en un caso ideal. De todos modos, el esquema balanceado podría presentar este rechazo sin más que añadir una etapa diferencial a su salida. Esta etapa puede tener un esquema simple, y no es necesario que sea de bajo ruido debido a que su influencia en la figura de ruido del sistema se ve atenuada por la ganancia de la primera etapa balanceada. Los dos tipos de esquemas descritos han sido diseñados y se van a presentar en las siguientes secciones. </span> </div><div style="text-align: justify;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgo6X2hQyuECvaUddGxrVlO8kLtKI5TGLk52ZN-_NIem9dMTK5EjCwr8cqf7aEBfhEBkHp6fCEDxouuryoWIZAaveqRtWS75dYLKzPxj2jTEuHVeJpDkCmTaMLqimCTCCaRoEkk7w0dBXc/s1600/2.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="242" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgo6X2hQyuECvaUddGxrVlO8kLtKI5TGLk52ZN-_NIem9dMTK5EjCwr8cqf7aEBfhEBkHp6fCEDxouuryoWIZAaveqRtWS75dYLKzPxj2jTEuHVeJpDkCmTaMLqimCTCCaRoEkk7w0dBXc/s400/2.bmp" width="400" /></a></div><div style="text-align: justify;"><br />
</div><div style="text-align: justify;"><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;"></span></b></div><div style="text-align: justify;"><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;">III. DISEÑO DE LOS AMPLIFICADORES DIFERENCIALES DE BAJO RUIDO </span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">A. Esquema diferencial </span></b> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">El esquema del amplificador diferencial con fuente de corriente común se muestra en la Fig. 2. Se ha realizado en tecnología microstrip, con substrato de permitividad εr=2.7 y espesor H=1mm. El circuito se ha construido colocando en cascada dos etapas diferenciales simples. Entre ambas etapas diferenciales se ha colocado una red RLC de adaptación. El diseño de esta red supone un compromiso entre conseguir una buena adaptación y disminuir la figura de ruido en toda la banda. Las bobinas de choque se han formado colocando varias bobinas de valores distintos en serie para garantizar un aislamiento correcto de la red de polarización respecto a la red de señal en todo el ancho de banda de funcionamiento. Del mismo modo, se han colocado varios condensadores en paralelo en la red de polarización para evitar que picos transitorios de voltaje que se produzcan en esta red se acoplen en las etapas de señal. Los transistores utilizados son FETs de bajo ruido del modelo ATF-34143 de Agilent. </span> </div><div style="text-align: justify;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEibEtbaVH_H6Z-e-Pr-VUQWjwrQd-qb89JAmHsuZYRBFY0L7mWEL5rsdhb-7jdg-CBvGjKWEScjmz0xzPtv6LNkdRxe6PHgwMsncT5LLv8VbeOkl1acGMx8R_fc-IWKYUxGS9KpVeC-qqY/s1600/3.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEibEtbaVH_H6Z-e-Pr-VUQWjwrQd-qb89JAmHsuZYRBFY0L7mWEL5rsdhb-7jdg-CBvGjKWEScjmz0xzPtv6LNkdRxe6PHgwMsncT5LLv8VbeOkl1acGMx8R_fc-IWKYUxGS9KpVeC-qqY/s400/3.bmp" width="282" /></a></div><div style="text-align: justify;"><br />
</div><div style="text-align: justify;"><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;">B. Esquema balanceado </span></b><br />
<b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;"> </span></b> </div><div style="text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;">El diseño del amplificador balanceado de bajo ruido (placa de circuito impreso y esquemático circuital) se presenta en la Fig. 3. Ha sido diseñado también en tecnología microstrip, con substrato de permitividad εr=3.4 y espesor H=1mm, y está formado por dos amplificadores independientes e idénticos. Cada amplificador consta de tres etapas en fuente común situadas en cascada. La adaptación entre etapas se realiza mediante una resistencia en serie, entre el drenador de una etapa y la puerta de la siguiente. La alimentación de cada etapa se realiza mediante un transistor bipolar autopolarizado. Igual que en el caso anterior, se han añadido varias bobinas de choque en serie, para aislar la red de alimentación, y varios condensadores en paralelo a tierra, para eliminar picos de voltaje en las etapas de amplificación. Los transistores utilizados en los amplificadores son FETs de bajo ruido, modelo ATF-34143 de Agilent. </span> </div><div style="text-align: justify;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEieMa9XN17fgtgMjP_HBpiK2Qcc8Hfgg7-KGNuBZZNQYWH2DwuTtZR7S_uZuioqEpw04TFSSmzwvWMC_e-62jGmmRoE5DukiibSoMMP89kLInzTTH823I2L9y-qd1IiE0XF_pbyINIw3TY/s1600/4.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="307" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEieMa9XN17fgtgMjP_HBpiK2Qcc8Hfgg7-KGNuBZZNQYWH2DwuTtZR7S_uZuioqEpw04TFSSmzwvWMC_e-62jGmmRoE5DukiibSoMMP89kLInzTTH823I2L9y-qd1IiE0XF_pbyINIw3TY/s400/4.bmp" width="400" /></a></div><div style="text-align: justify;"><br />
</div><div style="text-align: justify;"><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;">C. Resultados simulados </span></b> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Los resultados simulados de los dos amplificadores descritos anteriormente se muestran en Fig. 4 y Fig. 5 respectivamente. El software utilizado para la simulación ha sido el AWR Microwave Office. Dichas simulaciones se han obtenido colocando baluns ideales en los puertos de entrada y de salida de los circuitos, transformando el dispositivo de cuatro puertos en uno de dos. En la banda de trabajo, de 300MHz a 1GHz, se obtienen ganancias superiores a 28dB con el primer diseño y a 45dB con el segundo. Por su parte, la figura de ruido es inferior a 1.6dB y a 1.4dB para cada diseño respectivamente. Hay que tener en cuenta que las anteriores características se han obtenido suponiendo una impedancia de entrada de 50Ω. Si se modifica la impedancia de entrada a 150Ω, que es la esperada para la antena que se va a utilizar, estos valores de ganancia y ruido variarían. En concreto, modificando la impedancia a 150Ω, obtendríamos ganancias superiores a 28dB y 45dB en cada caso, y figuras de ruido inferiores a 0.7dB y 0.65dB respectivamente. </span></div><div style="text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;"> </span> </div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh3PmAmAjZGSE-toyRqhFE4U3olhCsYFUBjPbL8wR9dTq9EMSoT5Xyu8US8Q3-VESvhyE1iCqTcRKtb8Kg3iT5nzMKDBPfGUNUJqHrmE6xDOAUHMKS4e9ZWYvpPO_q89e0HZCs_ERZNw1E/s1600/5.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh3PmAmAjZGSE-toyRqhFE4U3olhCsYFUBjPbL8wR9dTq9EMSoT5Xyu8US8Q3-VESvhyE1iCqTcRKtb8Kg3iT5nzMKDBPfGUNUJqHrmE6xDOAUHMKS4e9ZWYvpPO_q89e0HZCs_ERZNw1E/s400/5.bmp" width="281" /></a></div><div style="text-align: justify;"><br />
<b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; font-size: small;">IV. CARACTERIZACIÓN DEL RUIDO DEL RECEPTOR </span></b> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Una vez se han presentado las características de ganancia y de ruido de los amplificadores por separado, el siguiente paso es caracterizar el sistema completo, integrando la antena junto al amplificador. El elemento radiante es una antena de tipo bunny-ear. Este tipo de antenas tienen dos puertos en salida diferencial, que se conectarán a las entradas del amplificador diferencial de bajo ruido. La caracterización de esta antena se ha realizado teniendo en cuenta el acoplo mutuo con otros elementos al colocarlos en un array. Por lo tanto, se han obtenido diferentes impedancias de la antena en función del ángulo de escaneo del array. Para realizar las simulaciones, se ha transformado la impedancia de la antena a un puerto utilizando un balun ideal (Fig. 6 (a)), ya que es imprescindible tener un dispositivo con un puerto de entrada y un puerto de salida para caracterizar la figura de ruido del sistema. A continuación se ha introducido esta impedancia en el puerto de entrada del esquema de la Fig. 6 (b), que simula el receptor completo. Además se han introducido dos resistencias de padding de 3kΩ en los puertos de la antena, que se han tenido en cuenta en la simulación. </span> </div><div style="text-align: justify;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg6MNyd6oxV0alJMiulVOq-OlDd3LKPMY6Y1lzVEDdX7vJyFyYwuTd4evOS68VCjdtNEqNgFU6Z2rgEejPAXRv-LnI1zy8ux2B03i2Bp3fLepKRVx8atOdr-CZAZX7TASRfeoC8kIQCzvU/s1600/6.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="371" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg6MNyd6oxV0alJMiulVOq-OlDd3LKPMY6Y1lzVEDdX7vJyFyYwuTd4evOS68VCjdtNEqNgFU6Z2rgEejPAXRv-LnI1zy8ux2B03i2Bp3fLepKRVx8atOdr-CZAZX7TASRfeoC8kIQCzvU/s400/6.bmp" width="400" /></a></div><div style="text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;">La caracterización de ruido se ha realizado usando la temperatura equivalente de ruido Te. Este parámetro se puede calcular como </span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjPG3adtYhKRSxDnV5gEEP9exW15St582MFHMJ3hr7nN71N9J85z5DLaMQyi6D9UdUQ2uM75DJdkrOliY-7QIMcV0NGp_qs-2Bk7lrgNo3fKdBb3G2zFa69RWa-EcP8bFH28LnPhXubj5U/s1600/7.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjPG3adtYhKRSxDnV5gEEP9exW15St582MFHMJ3hr7nN71N9J85z5DLaMQyi6D9UdUQ2uM75DJdkrOliY-7QIMcV0NGp_qs-2Bk7lrgNo3fKdBb3G2zFa69RWa-EcP8bFH28LnPhXubj5U/s320/7.bmp" /></a></div><div style="text-align: justify;"><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">donde T0 es la temperatura standard en Kelvin (290K), y NF es el factor de ruido. Esta medida usa los valores de la impedancia de la fuente para calcular el factor de ruido. </span> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Las gráficas de la temperatura de ruido del sistema usando el amplificador balanceado y el amplificador diferencial, para diferentes ángulos de escaneo del array de antenas (0rad, 0.4rad y 0.8rad), se presentan en la Fig. 7 y en la Fig. 8 respectivamente. Se han obtenido valores de temperatura equivalente de ruido entorno a 60K (NF=0.8dB) con ambos tipos de amplificadores. Para ángulo de escaneo de 0º (broadside), la temperatura de ruido no supera los 90K (NF=1.2dB) para el esquema diferencial y los 67K (NF=0.9dB) para el esquema balanceado. </span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEguC2t_fE_Vkds4duepMTQmH2W06uEHQUT9OJAHRVECope3oMqgO84nX8NK30MMfUUduJT3Cr0YWlrQM6yRAlmwi3RWyPDT_pJZ4nA_VQx5mMpG_jcF1mJcrjsi1fck-y7F0A5ZU29_lec/s1600/8.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEguC2t_fE_Vkds4duepMTQmH2W06uEHQUT9OJAHRVECope3oMqgO84nX8NK30MMfUUduJT3Cr0YWlrQM6yRAlmwi3RWyPDT_pJZ4nA_VQx5mMpG_jcF1mJcrjsi1fck-y7F0A5ZU29_lec/s400/8.bmp" width="270" /></a></div><div style="text-align: justify;"><br />
<b><span style="color: #93c47d; font-family: Verdana, sans-serif; font-size: small;">V. CONCLUSIONES </span></b> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">En este artículo se han presentado los amplificadores diferenciales de microondas como una opción eficiente para el desarrollo de sistemas receptores de bajo ruido. Además añaden ventajas intrínsecas a la topología, como el rechazo de señales interferentes. Estas propiedades son especialmente críticas en sistemas de radioastronomía, que es la aplicación para la que se han desarrollado los dispositivos presentados. Concretamente se han descrito y diseñado dos modelos diferentes, uno basado en un esquema balanceado y el otro basado en un esquema diferencial. Se ha demostrado que es posible obtener altos valores de ganancia y bajos niveles de ruido para anchos de banda de funcionamiento grandes (en este caso el diseño funcionaba entre 300MHz y 1GHz). La rigurosidad con la que se han realizado las simulaciones nos hace ser optimistas de cara a poder replicar los resultados simulados con la implementación real de los circuitos que está en proceso. </span> <br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Hernández Caballero Indiana</span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Asignatura: CAF</span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Fuente: <a href="http://www.tsc.uc3m.es/~ogarpe/index_archivos/ursi2008madrid.pdf">http://www.tsc.uc3m.es/~ogarpe/index_archivos/ursi2008madrid.pdf</a></span></div></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-44055691227074661402010-07-25T23:13:00.002-04:302010-07-27T16:48:45.754-04:30Un amplificador operacional equilibrado<div class="post-header"></div><div class="post-body entry-content"><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_filelist.xml" rel="File-List"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_themedata.thmx" rel="themeData"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_colorschememapping.xml" rel="colorSchemeMapping"></link> <style>
<!-- /* Font Definitions */ @font-face {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4; mso-font-charset:0; mso-generic-font-family:roman; mso-font-pitch:variable; mso-font-signature:-1610611985 1107304683 0 0 159 0;} @font-face {font-family:Calibri; panose-1:2 15 5 2 2 2 4 3 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:-1610611985 1073750139 0 0 159 0;} @font-face {font-family:Verdana; panose-1:2 11 6 4 3 5 4 4 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:536871559 0 0 0 415 0;} @font-face {font-family:TimesNewRoman; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 0 0 0 1 0;} @font-face {font-family:"TimesNewRoman\,BoldItalic"; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 0 0 0 1 0;} @font-face {font-family:"TimesNewRoman\,Bold"; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 0 0 0 1 0;} @font-face {font-family:"TimesNewRoman\,Italic"; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 0 0 0 1 0;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {mso-style-unhide:no; mso-style-qformat:yes; mso-style-parent:""; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:0cm; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} p.MsoListParagraph, li.MsoListParagraph, div.MsoListParagraph {mso-style-priority:34; mso-style-unhide:no; mso-style-qformat:yes; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:36.0pt; mso-add-space:auto; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} p.MsoListParagraphCxSpFirst, li.MsoListParagraphCxSpFirst, div.MsoListParagraphCxSpFirst {mso-style-priority:34; mso-style-unhide:no; mso-style-qformat:yes; mso-style-type:export-only; margin-top:0cm; margin-right:0cm; margin-bottom:0cm; margin-left:36.0pt; margin-bottom:.0001pt; mso-add-space:auto; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} p.MsoListParagraphCxSpMiddle, li.MsoListParagraphCxSpMiddle, div.MsoListParagraphCxSpMiddle {mso-style-priority:34; mso-style-unhide:no; mso-style-qformat:yes; mso-style-type:export-only; margin-top:0cm; margin-right:0cm; margin-bottom:0cm; margin-left:36.0pt; margin-bottom:.0001pt; mso-add-space:auto; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} p.MsoListParagraphCxSpLast, li.MsoListParagraphCxSpLast, div.MsoListParagraphCxSpLast {mso-style-priority:34; mso-style-unhide:no; mso-style-qformat:yes; mso-style-type:export-only; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:36.0pt; mso-add-space:auto; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoPapDefault {mso-style-type:export-only; margin-bottom:10.0pt; line-height:115%;} @page Section1 {size:612.0pt 792.0pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} /* List Definitions */ @list l0 {mso-list-id:517013624; mso-list-type:hybrid; mso-list-template-ids:-1475589022 1614339346 201981977 201981979 201981967 201981977 201981979 201981967 201981977 201981979;} @list l0:level1 {mso-level-number-format:roman-upper; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:71.4pt; text-indent:-36.0pt;} @list l0:level2 {mso-level-number-format:alpha-lower; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:89.4pt; text-indent:-18.0pt;} @list l1 {mso-list-id:1597711268; mso-list-type:hybrid; mso-list-template-ids:-879076552 201981973 201981977 201981979 201981967 201981977 201981979 201981967 201981977 201981979;} @list l1:level1 {mso-level-number-format:alpha-upper; mso-level-tab-stop:none; mso-level-number-position:left; margin-left:53.4pt; text-indent:-18.0pt;} ol {margin-bottom:0cm;} ul {margin-bottom:0cm;} -->
</style> <span style="font-size: x-small;"><br />
</span> <br />
<div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><i><span style="font-family: Verdana, sans-serif;">Resumen</span></i><span style="font-family: Verdana, sans-serif;">— Se presenta un amplificador operacional completamente equilibrado, que opera sobre señales de modo común y de modo diferencial. A diferencia de los amplificadores operacionales completamente diferenciales estándar, en los cuales su comportamiento de modo común está fijado por un lazo interno, el amplificador propuesto permite analizar y diseñar tanto la respuesta de modo diferencial de un circuito como su respuesta de modo común. El dispositivo puede implementarse en forma monolítica o utilizando amplificadores operacionales estándar. Su estructura puede reconocerse en diversos circuitos completamente diferenciales (F-D: "</span><i><span style="font-family: Verdana, sans-serif;">Fully-Differential"</span></i><span style="font-family: Verdana, sans-serif;">) clásicos, lo cual permite analizarlos en un nuevo contexto, así también como diseñar nuevos circuitos de aplicación, asegurando tanto su respuesta de modo común como de modo diferencial.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Se presentan algunas aplicaciones en el análisis de circuitos FD clásicos y el diseño e implementación de un oscilador F-D que oscila en modo común y en modo diferencial a dos frecuencias independientes.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><i><span style="font-family: Verdana, sans-serif;">Palabras clave </span></i><span style="font-family: Verdana, sans-serif;">— Amplificador operacional, procesamiento analógico, amplificadores diferenciales.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoListParagraph" style="margin-left: 71.4pt; text-align: justify; text-indent: -36pt;"><span style="font-size: x-small;"><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif; line-height: 115%;">I.<span style="font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; line-height: normal;"> </span></span></b><span style="font-family: Verdana, sans-serif; line-height: 115%;"><b style="color: #93c47d;">INTRODUCCIÓN</b></span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Los circuitos completamente diferenciales (F-D: "</span><i><span style="font-family: Verdana, sans-serif;">Fully- Differential Circuits"</span></i><span style="font-family: Verdana, sans-serif;">) son muy utilizados actualmente</span><i><span style="font-family: Verdana, sans-serif;"> </span></i><span style="font-family: Verdana, sans-serif;">por a su alta inmunidad a perturbaciones de modo común</span><i><span style="font-family: Verdana, sans-serif;"> </span></i><span style="font-family: Verdana, sans-serif;">y por su mayor excursión de la señal. En efecto, un circuito FD</span><i><span style="font-family: Verdana, sans-serif;"> </span></i><span style="font-family: Verdana, sans-serif;">admite, para la misma tensión de alimentación, el doble de excursión que su contraparte </span><i><span style="font-family: Verdana, sans-serif;">single-ended </span></i><span style="font-family: Verdana, sans-serif;">(S-E). Esto último</span><i><span style="font-family: Verdana, sans-serif;"> </span></i><span style="font-family: Verdana, sans-serif;">es particularmente importante en equipos alimentados a</span><i><span style="font-family: Verdana, sans-serif;"> </span></i><span style="font-family: Verdana, sans-serif;">baterías, donde la tensión de alimentación es un recurso escaso a preservar.</span><i><span style="font-family: Verdana, sans-serif;"></span></i></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Por otra parte, los circuitos F-D pueden conectarse en forma directa a los convertidores analógicos digitales actuales de alta resolución, que en su mayoría tienen entradas de tipo diferencial; resultando así circuitos de acondicionamiento simples y elegantes [1].</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Existen dispositivos comerciales para la implementación de circuitos F-D como los FDOA: </span><i><span style="font-family: Verdana, sans-serif;">"Fully-Differential Operational Amplifiers" </span></i><span style="font-family: Verdana, sans-serif;">[2], pero sólo permiten implementar topologías del tipo inversor. Si se requiere un amplificador noinversor, por ejemplo para conservar una alta impedancia de </span><i><span style="font-family: Verdana, sans-serif;">Difference Amplifier</span></i><span style="font-family: Verdana, sans-serif;">". Estos dispositivos amplifican la diferencia entre dos señales diferenciales y proporcionan una mayor flexibilidad de diseño [3,4]. Tanto el FDAO como el FDDA presentan una limitación: operan sobre señales de modo diferencial mientras que su respuesta de modo común es determinada por un lazo de realimentación interno (CMFB: "</span><i><span style="font-family: Verdana, sans-serif;">Common Mode Feedback"</span></i><span style="font-family: Verdana, sans-serif;">), el cual no es accesible para el diseñador de aplicaciones. Este lazo interno puede interactuar con la red de realimentación externa dando lugar a problemas de estabilidad [5].</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">El diseño de circuitos F-D se realiza usualmente partiendo de un prototipo S-E. Es decir, se diseña un circuito S-E utilizando técnicas clásicas y luego se lo transforma en F-D replicando el circuito S-E tomando el común (masa) como eje de simetría [6]. Como puede advertirse, esta estrategia contempla exclusivamente la respuesta de modo diferencial del circuito F-D, (que coincidirá con la del prototipo S-E), pero nada asegura acerca de la respuesta de modo común. Esta última puede resultar inapropiada o incluso inestable [6].</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Existe un método, basado en una descripción en variables de estado, que permite diseñar tanto la respuesta de modo común como de modo diferencial de un circuito F-D [7], pero el mismo se aparta de las técnicas habitualmente utilizadas por los diseñadores de circuitos analógicos.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">En este trabajo se propone un método de análisis y diseño de circuitos F-D que se basa en definir un amplificador operacional equilibrado (FBOA: "</span><i><span style="font-family: Verdana, sans-serif;">Fully-Balanced Operational</span></i><span style="font-family: Verdana, sans-serif;"> </span><i><span style="font-family: Verdana, sans-serif;">Amplifier</span></i><span style="font-family: Verdana, sans-serif;">"). La técnica propuesta, que contempla tanto la respuesta de modo común como de modo diferencial, permite analizar circuitos F-D existentes, así también como diseñar nuevas aplicaciones.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoListParagraphCxSpFirst" style="line-height: normal; margin: 0cm 0cm 0.0001pt 71.4pt; text-align: justify; text-indent: -36pt;"><span style="font-size: x-small;"><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">II.<span style="font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; line-height: normal;"> </span></span></b><span style="font-family: Verdana, sans-serif;"><b style="color: #93c47d;">EL AMPLIFICADOR OPERACIONAL EQUILIBRADO</b></span></span></div><div class="MsoListParagraphCxSpLast" style="line-height: normal; margin: 0cm 0cm 0.0001pt 71.4pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Un esquema del amplificador operacional propuesto se muestra en la Fig.1. El mismo posee dos entradas equilibradas (una inversora y otra no-inversora) y una salida equilibrada.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Las tensiones de modo diferencial (MD) y de modo común (MC) en la entrada inversora se denotan como (</span><i><span style="font-family: Verdana, sans-serif;">v</span></i><sub><span style="font-family: Verdana, sans-serif;">iD</span></sub><span style="font-family: Verdana, sans-serif;">-, </span><i><span style="font-family: Verdana, sans-serif;">v</span></i><sub><span style="font-family: Verdana, sans-serif;">iC</span></sub><span style="font-family: Verdana, sans-serif;">-) y las correspondientes a la entrada no-inversora como (</span><i><span style="font-family: Verdana, sans-serif;">v</span></i><sub><span style="font-family: Verdana, sans-serif;">iD</span></sub><span style="font-family: Verdana, sans-serif;">+, </span><i><span style="font-family: Verdana, sans-serif;">v</span></i><sub><span style="font-family: Verdana, sans-serif;">iC</span></sub><span style="font-family: Verdana, sans-serif;">+). Las tensiones de salida son (</span><i><span style="font-family: Verdana, sans-serif;">v</span></i><sub><span style="font-family: Verdana, sans-serif;">oD</span></sub><span style="font-family: Verdana, sans-serif;">, </span><i><span style="font-family: Verdana, sans-serif;">v</span></i><sub><span style="font-family: Verdana, sans-serif;">oC</span></sub><span style="font-family: Verdana, sans-serif;">).</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj7gLeZb4E0FqOZBvLHPfdj_CdJpRd4jyYGnnMCMWdnhlBVnTKbAu6znJ42u0fyDc_kN2-LquVwpoeN_NH_LTM-MKWbc3y7LIHtgGMyPen3DQYBDQMPchsJbcE7xMTtuMx1zF_hFgY-BBQ/s1600/1.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="180" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj7gLeZb4E0FqOZBvLHPfdj_CdJpRd4jyYGnnMCMWdnhlBVnTKbAu6znJ42u0fyDc_kN2-LquVwpoeN_NH_LTM-MKWbc3y7LIHtgGMyPen3DQYBDQMPchsJbcE7xMTtuMx1zF_hFgY-BBQ/s320/1.bmp" width="320" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">A diferencia del FDAO y del FDDA, que amplifican exclusivamente tensiones de modo diferencial, el FBOA propuesto amplifica tanto las señales de modo común como las de modo diferencial. La relación entre sus entradas y salidas están dadas por:</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEheY1WBFIGPZ0bZRBZ-xi4Oepa2jGcLSK-uG8K9KoZn6xcNG1wNxUuUGzuP4YvZ65zi2Fs62lvJ36uzaCUYSJ3p-oW7bexu_mMwU3oWksCFCYEsNVlzSGY6jSk7tDr841X4F6sw11T9OG4/s1600/2.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEheY1WBFIGPZ0bZRBZ-xi4Oepa2jGcLSK-uG8K9KoZn6xcNG1wNxUuUGzuP4YvZ65zi2Fs62lvJ36uzaCUYSJ3p-oW7bexu_mMwU3oWksCFCYEsNVlzSGY6jSk7tDr841X4F6sw11T9OG4/s320/2.bmp" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Un amplificador operacional está concebido para operar realimentado y su ganancia es idealmente infinita. Esto implica:</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjdoQaG9wH0Dmo6KRHLw5Dh8oBeJef8YfavijEsxapi0snd0hkpCL_wJSHWTlPYVEySb8y3O3NRMVRZ31GGS6MCGVa_cpxB9wQu3GVIY74WilsxSqPO17wZBmXU3PlZL5I6AJFBZBCz944/s1600/3.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjdoQaG9wH0Dmo6KRHLw5Dh8oBeJef8YfavijEsxapi0snd0hkpCL_wJSHWTlPYVEySb8y3O3NRMVRZ31GGS6MCGVa_cpxB9wQu3GVIY74WilsxSqPO17wZBmXU3PlZL5I6AJFBZBCz944/s320/3.bmp" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Es decir que el conocido concepto de "tierra virtual" puede aplicarse para ambos modos, proporcionando un camino simple para el análisis de circuitos F-D. </span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoListParagraphCxSpFirst" style="line-height: normal; margin: 0cm 0cm 0.0001pt 53.4pt; text-align: justify; text-indent: -18pt;"><span style="font-size: x-small;"><b style="color: #93c47d;"><span style="font-family: Verdana, sans-serif;">A.<span style="font-family: 'Times New Roman'; font-style: normal; font-variant: normal; font-weight: normal; line-height: normal;"> </span></span></b><span style="font-family: Verdana, sans-serif;"><b style="color: #93c47d;">Implementación del FBOA.</b></span><i><span style="font-family: Verdana, sans-serif;"></span></i></span></div><div class="MsoListParagraphCxSpLast" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">El FBOA puede construirse como un circuito integrado dedicado, pero también puede implementarse fácilmente utilizando amplificadores operacionales convencionales (S-E) conectándolos según se muestra la Fig.2. Es simple demostrar que este circuito funciona verificando la ecuación (1).</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhAhduwROf99lIW13Nn7i0b0nC5WYL5sIbW49HTDuGJPa-tpOnjmazi9K04iqOtWRUzxc4KgbTjZbjkUKC5RHNNrLYB4QFpRS-v7CJRIWq_EipuA0-hQWP8SeUfylMW3lK9CQg8BeeTi-c/s1600/4.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="166" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhAhduwROf99lIW13Nn7i0b0nC5WYL5sIbW49HTDuGJPa-tpOnjmazi9K04iqOtWRUzxc4KgbTjZbjkUKC5RHNNrLYB4QFpRS-v7CJRIWq_EipuA0-hQWP8SeUfylMW3lK9CQg8BeeTi-c/s400/4.bmp" width="400" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">La estructura presentada en la Fig.2 puede reconocerse en diversos circuitos F-D clásicos, los cuales, como se mostrará a continuación, pueden analizarse utilizando el concepto de FBOA.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify; text-indent: 35.4pt;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;"><b style="color: #93c47d;">III. ANÁLISIS DE CIRCUITOS F-D.</b></span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">El método de análisis consiste en, dado un circuito F-D, identificar los FBOA y las realimentaciones del circuito; caracterizarlas y posteriormente analizar el comportamiento para cada modo (MC y MD) por separado. Como se mostró anteriormente, el concepto de tierra virtual puede aplicarse tanto para MD como para MC, lo cual permite resolver fácilmente circuitos basados en A.O. realimentados.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify; text-indent: 35.4pt;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;"><b style="color: #93c47d;">A. Ejemplo de análisis.</b></span><i><span style="font-family: Verdana, sans-serif;"></span></i></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">En la Fig.3 (a) se presenta el conocido amplificador F-D de dos A.O. , el cual compone la etapa de entrada del aun más conocido amplificador de instrumentación de tres A.O. [1]. Este circuito puede redibujarse considerando que los dos A.O. componen un FBOA (ver Fig.2.). El circuito resultante, que se muestra en la Fig.3(b), es totalmente equivalente al primero, pero permite identificar más claramente los bloques de comparación, amplificación y realimentación.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhOJeV_TO7aHrbwIqQfCNGqz2nfp8HVazIKX_DIDGDmBHSy-CIj9RuLzMH1nflos177V5Sr_mwjHT9LHz2_kknXkrpfZKzCOdB7RKDOE5gz2Tq9jHq1OP9UQGX3lRcqYa_jKvQoL37mp-k/s1600/5.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="237" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhOJeV_TO7aHrbwIqQfCNGqz2nfp8HVazIKX_DIDGDmBHSy-CIj9RuLzMH1nflos177V5Sr_mwjHT9LHz2_kknXkrpfZKzCOdB7RKDOE5gz2Tq9jHq1OP9UQGX3lRcqYa_jKvQoL37mp-k/s400/5.bmp" width="400" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">La red de realimentación es un atenuador F-D que presenta una ganancia </span><span style="font-family: Verdana, sans-serif;">β</span><span style="font-family: Verdana, sans-serif;">D para señales de modo diferencial y una ganancia </span><span style="font-family: Verdana, sans-serif;">β</span><span style="font-family: Verdana, sans-serif;">C para señales de modo común. Las mismas están dadas por:</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjUS6tgEoYYguNhCJO_gE_xEcdnGmtrXalXxsEyJI_nnkGbJ6b766VHW3eDhqVf3jh3TXmxK0BTXm_ukIc3dTL80M32WThJ83uQ1OyVNAc13W4rEhY0paCzeR1Rxz75Xt9yCT-jsaAZFyc/s1600/6.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjUS6tgEoYYguNhCJO_gE_xEcdnGmtrXalXxsEyJI_nnkGbJ6b766VHW3eDhqVf3jh3TXmxK0BTXm_ukIc3dTL80M32WThJ83uQ1OyVNAc13W4rEhY0paCzeR1Rxz75Xt9yCT-jsaAZFyc/s320/6.bmp" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Se observa que esta red atenúa las tensiones de MD mientras que presenta una ganancia unitaria para tensiones de MC. Considerando que el circuito de la Fig.3.(b) corresponde a una configuración no-inversora, resultan los circuitos equivalentes para MC y MD que se indican en la Fig. 4 (a) y Fig.4 (b) respectivamente.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjSe-vD_ydqBXFky-nmdkv-xzU2Qq9ZpLiL4NIxjjNpRhoQIvUkTgJFjX-3rWq4vrckP0A3MXCsv0OKakw1a3Lvknuni-GZnMB-xWjaLtm5YR6grwhwlprgYQ_tCsLT9Ipxv7JeaSnyyUo/s1600/7.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="192" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjSe-vD_ydqBXFky-nmdkv-xzU2Qq9ZpLiL4NIxjjNpRhoQIvUkTgJFjX-3rWq4vrckP0A3MXCsv0OKakw1a3Lvknuni-GZnMB-xWjaLtm5YR6grwhwlprgYQ_tCsLT9Ipxv7JeaSnyyUo/s400/7.bmp" width="400" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">A partir de estos circuitos se pueden obtener las ganancias de modo cerrado de modo diferencial </span><i><span style="font-family: Verdana, sans-serif;">G</span></i><sub><span style="font-family: Verdana, sans-serif;">DD</span></sub><span style="font-family: Verdana, sans-serif;">=</span><i><span style="font-family: Verdana, sans-serif;">v</span></i><sub><span style="font-family: Verdana, sans-serif;">oD</span></sub><span style="font-family: Verdana, sans-serif;">/</span><i><span style="font-family: Verdana, sans-serif;">v</span></i><sub><span style="font-family: Verdana, sans-serif;">iD</span></sub><span style="font-family: Verdana, sans-serif;"> y la de modo común </span><i><span style="font-family: Verdana, sans-serif;">G</span></i><sub><span style="font-family: Verdana, sans-serif;">CC</span></sub><span style="font-family: Verdana, sans-serif;">=</span><i><span style="font-family: Verdana, sans-serif;">v</span></i><sub><span style="font-family: Verdana, sans-serif;">oC</span></sub><span style="font-family: Verdana, sans-serif;">/</span><i><span style="font-family: Verdana, sans-serif;">v</span></i><sub><span style="font-family: Verdana, sans-serif;">oC</span></sub><span style="font-family: Verdana, sans-serif;"> [1], las cuales están dadas por:</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhbrr3Lt68BTKAXIqwdtxcXnkhy4a1gWR-x4ngvsOhQGSatmrEQiymBGsaEIc8E6ziw8OyAP1-cSCDh_zPNvKctwvRKpw1mYhsrl2y_R224xjZ-OwXfpF6RG5g2njt1B4U2pcWJd8-rUsA/s1600/8.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhbrr3Lt68BTKAXIqwdtxcXnkhy4a1gWR-x4ngvsOhQGSatmrEQiymBGsaEIc8E6ziw8OyAP1-cSCDh_zPNvKctwvRKpw1mYhsrl2y_R224xjZ-OwXfpF6RG5g2njt1B4U2pcWJd8-rUsA/s320/8.bmp" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Un resultado no tan obvio y difícil de advertir en el circuito de la Fig.3.(a), puede desprenderse fácilmente del circuito de MC de la Fig.4 (b): si bien la ganancia diferencial del amplificador puede ser mucho mayor que la unidad, los A.O deben se estables para ganancia unitaria; de lo contrario el circuito no será estable para tensiones de MC [8]. Este inconveniente suele presentarse frecuentemente en la implementación de amplificadores de instrumentación de gran ancho de banda.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify; text-indent: 35.4pt;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;"><b style="color: #93c47d;">IV. DISEÑO DE CIRCUITOS F-D.</b></span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">La técnica de diseño propuesta para circuitos F-D es similar a las habitualmente utilizadas para circuitos </span><i><span style="font-family: Verdana, sans-serif;">singleended</span></i><span style="font-family: Verdana, sans-serif;">. La misma consiste en reemplazar los A.O. por FBOA y en considerar tanto las realimentaciones de MD como las de MC. Como ejemplo de aplicación y para mostrar la posibilidad de diseñar en forma independiente la dinámica de modo común y de modo diferencial, se presenta a continuación el diseño de un oscilador. Como primer paso se diseña el oscilador S-E. En este caso se optó por un oscilador de doble integrador que se muestra en la Fig.5.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_QHUGMOJe2RnhLWRnZN40m3kXcdu05OL804lPZlUCu_ySTXa5QTyPJzG2PlBSBwIPEqMvU45FE8hEA8iB_5ETWOMZbCB0XhIVwRfBBSpRmQnr1jUkdXki-8hZI7lYAddwbRAqjUQtVY4/s1600/9.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="206" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_QHUGMOJe2RnhLWRnZN40m3kXcdu05OL804lPZlUCu_ySTXa5QTyPJzG2PlBSBwIPEqMvU45FE8hEA8iB_5ETWOMZbCB0XhIVwRfBBSpRmQnr1jUkdXki-8hZI7lYAddwbRAqjUQtVY4/s400/9.bmp" width="400" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">La frecuencia de oscilación de este circuito queda determinada por la realimentación </span><span style="font-family: Verdana, sans-serif;">β</span><span style="font-family: Verdana, sans-serif;">1, al cual está dada por:</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgr4iRLYHRxKqMB27AEvMkel-YccAwxpC9rajb3OZda7uuRXxJ6GfR5aNxWA0IFBVNSOyTiycg5_0o8AIV0TAsoSnG_Y5oopT_m7L2cd45seWGakQ0jb1VQWq6Ci83N464Z1FtPQ2ftRRM/s1600/10.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgr4iRLYHRxKqMB27AEvMkel-YccAwxpC9rajb3OZda7uuRXxJ6GfR5aNxWA0IFBVNSOyTiycg5_0o8AIV0TAsoSnG_Y5oopT_m7L2cd45seWGakQ0jb1VQWq6Ci83N464Z1FtPQ2ftRRM/s320/10.bmp" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">La segunda realimentación </span><span style="font-family: Verdana, sans-serif;">β</span><sub><span style="font-family: Verdana, sans-serif;">2</span></sub><span style="font-family: Verdana, sans-serif;"> se incluye para ubicar los polos ligeramente en el semiplano derecho para asegurar así el arranque del oscilador. El circuito de la Fig.5 no incluye control de amplitud, la cual quedará determinada por no linealidades propias del circuito. El segundo paso consiste en reemplazar los A.O. por FBOA, y utilizar redes F-D para implementar las realimentaciones </span><span style="font-family: Verdana, sans-serif;">β</span><sub><span style="font-family: Verdana, sans-serif;">1</span></sub><span style="font-family: Verdana, sans-serif;">, </span><span style="font-family: Verdana, sans-serif;">β</span><sub><span style="font-family: Verdana, sans-serif;">2</span></sub><span style="font-family: Verdana, sans-serif;"> resultando el circuito de la Fig.6.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhorO8K5FojbrrxNZMe-w3aH9xjr7VUem9jPsY7dUT0iM88Bauu7xyt4wFB11NtDDBspevVt0kMnGTXBpp3SRqzFPIJeiJUqtTczcRax56QLNjop0dHbyV_1lH27cr-yIT3lBun2kqh92o/s1600/11.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="277" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhorO8K5FojbrrxNZMe-w3aH9xjr7VUem9jPsY7dUT0iM88Bauu7xyt4wFB11NtDDBspevVt0kMnGTXBpp3SRqzFPIJeiJUqtTczcRax56QLNjop0dHbyV_1lH27cr-yIT3lBun2kqh92o/s400/11.bmp" width="400" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">La red de realimentación </span><span style="font-family: Verdana, sans-serif;">β</span><sub><span style="font-family: Verdana, sans-serif;">1</span></sub><span style="font-family: Verdana, sans-serif;"> presenta una ganancia </span><span style="font-family: Verdana, sans-serif;">β</span><sub><span style="font-family: Verdana, sans-serif;">1D</span></sub><span style="font-family: Verdana, sans-serif;"> para tensiones de modo diferencial y una ganancia </span><span style="font-family: Verdana, sans-serif;">β</span><sub><span style="font-family: Verdana, sans-serif;">1C</span></sub><span style="font-family: Verdana, sans-serif;"> para tensiones de modo común. Si se considera que los resistores </span><i><span style="font-family: Verdana, sans-serif;">R</span></i><span style="font-family: Verdana, sans-serif;">C no cargan apreciablemente al atenuador </span><span style="font-family: Verdana, sans-serif;">β</span><sub><span style="font-family: Verdana, sans-serif;">1</span></sub><span style="font-family: Verdana, sans-serif;">, las ganancias de realimentación quedan dadas por:</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhI7_5DUlSHkH6ldkYNhG8oPSKa22JoBbl68heZHvNMfmjwK0jGIMcEwjb0PYuUJ2ruo5RQxhFW72_OCF8g-cV_r-pgTEahCQVCo_kCpMJ58Y3Da-ygFg6WaQHRD2cqpulD3lOukAtR-DM/s1600/12.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhI7_5DUlSHkH6ldkYNhG8oPSKa22JoBbl68heZHvNMfmjwK0jGIMcEwjb0PYuUJ2ruo5RQxhFW72_OCF8g-cV_r-pgTEahCQVCo_kCpMJ58Y3Da-ygFg6WaQHRD2cqpulD3lOukAtR-DM/s320/12.bmp" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Como la ganancia de realimentación de MD es distinta a la correspondiente al MC, el circuito presentará, de acuerdo a (5), dos frecuencias de oscilación: una de modo diferencial </span><i><span style="font-family: Verdana, sans-serif;">f</span></i><sub><span style="font-family: Verdana, sans-serif;">oD</span></sub><span style="font-family: Verdana, sans-serif;"> y otra de modo común </span><i><span style="font-family: Verdana, sans-serif;">f</span></i><sub><span style="font-family: Verdana, sans-serif;">oC</span></sub><span style="font-family: Verdana, sans-serif;">, cuyos valores son:</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEje29MqVi_59aJ0lQquNjlhN-fRQZVMK7O4i142f0kCWNQ_aOn2dIlTTI0QKbSO8QBDSV-REkBJrC9peqdTFaSQ3a5zaOGRL11ND6pT_aBhMjmoHXL-OlG_RU8ngaJua7jVAuvzIUHOaBo/s1600/13.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEje29MqVi_59aJ0lQquNjlhN-fRQZVMK7O4i142f0kCWNQ_aOn2dIlTTI0QKbSO8QBDSV-REkBJrC9peqdTFaSQ3a5zaOGRL11ND6pT_aBhMjmoHXL-OlG_RU8ngaJua7jVAuvzIUHOaBo/s320/13.bmp" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Para este ejemplo se adoptaron:</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgVu63wcDE8ZhBQ4OXp6y2eR0T7i8w9FZdyuODRZ6IGLHYmebKg5yQfHKiNSHnmy-ZujOtMoRCCIijn3WxE7-ZEQot8gNKoPczXRmQQX1QdG-WitjN5u_Bqah9fC6wTo60JS1sv647c-pw/s1600/14.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="86" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgVu63wcDE8ZhBQ4OXp6y2eR0T7i8w9FZdyuODRZ6IGLHYmebKg5yQfHKiNSHnmy-ZujOtMoRCCIijn3WxE7-ZEQot8gNKoPczXRmQQX1QdG-WitjN5u_Bqah9fC6wTo60JS1sv647c-pw/s400/14.bmp" width="400" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Resultando:</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;"><br />
</span></span></div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiz7hVNmbNd2RvP9m_SXRTBEeZ8HtzYaOpV51DU7mFOxuDcWYRpBfoMtHKp2V82GH_yhg27iwZJDPBa8rhEDrvdJOiLefb9BKyTnLBPPK32ZJ13Tte2lg_oPqTVAHH3naJ_KGTs-goc1oM/s1600/15.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="34" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiz7hVNmbNd2RvP9m_SXRTBEeZ8HtzYaOpV51DU7mFOxuDcWYRpBfoMtHKp2V82GH_yhg27iwZJDPBa8rhEDrvdJOiLefb9BKyTnLBPPK32ZJ13Tte2lg_oPqTVAHH3naJ_KGTs-goc1oM/s320/15.bmp" width="320" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;"><br />
</span></span></div><div class="MsoNormal" style="color: #93c47d; line-height: normal; margin-bottom: 0.0001pt; text-align: justify; text-indent: 35.4pt;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;"> </span><b><span style="font-family: Verdana, sans-serif;">V. RESULTADOS EXPERIMENTALES</span></b></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify; text-indent: 35.4pt;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;"></span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Para validar la técnica propuesta se construyó el oscilador diseñado en el punto previo y se comprobó que el mismo oscila en MC y en MD a frecuencias muy próximas a las predichas por (7). En la Fig.7 se muestran las tensiones en las salidas </span><i><span style="font-family: Verdana, sans-serif;">y</span></i><sub><span style="font-family: Verdana, sans-serif;">H</span></sub><span style="font-family: Verdana, sans-serif;">, </span><i><span style="font-family: Verdana, sans-serif;">y</span></i><sub><span style="font-family: Verdana, sans-serif;">L</span></sub><span style="font-family: Verdana, sans-serif;"> del circuito y en la Fig.8 se presentan las tensiones de salida de modo común </span><i><span style="font-family: Verdana, sans-serif;">y</span></i><sub><span style="font-family: Verdana, sans-serif;">C</span></sub><span style="font-family: Verdana, sans-serif;"> y de modo diferencial </span><i><span style="font-family: Verdana, sans-serif;">y</span></i><sub><span style="font-family: Verdana, sans-serif;">D</span></sub><span style="font-family: Verdana, sans-serif;">, donde se pueden observar más claramente las oscilaciones de M<sub>C</sub> y de M<sub>D</sub>.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;"></span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;"></span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;"></span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiQZu302JzVEL2iOK5-HN1RwJO4h9w2emE7tV7KNTKSppOtjdNEjVMXkCPlMBLhoMgjN_rGUythRTI4jjDKoymb_ryRUwCbEA9BxMmT8xUDDxR7zbtD7AzLD60U49zRIell5IhMQhHft7c/s1600/16.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="293" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiQZu302JzVEL2iOK5-HN1RwJO4h9w2emE7tV7KNTKSppOtjdNEjVMXkCPlMBLhoMgjN_rGUythRTI4jjDKoymb_ryRUwCbEA9BxMmT8xUDDxR7zbtD7AzLD60U49zRIell5IhMQhHft7c/s400/16.bmp" width="400" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="separator" style="clear: both; text-align: center;"><span style="font-size: x-small;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi5qL34ZrWf7-hq3cMF38eb0aWILcN3HQ_U20gdRHMc3C6ea5jzk5vlFg0Fv60j6W9yBBWjUO9bcVao9nF6CNgQ5OJnC9lelmhSTd9f2_UeDQQfP5A43Ws5uQhl0vub2EFUWKkrt2JdZmM/s1600/17.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="285" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi5qL34ZrWf7-hq3cMF38eb0aWILcN3HQ_U20gdRHMc3C6ea5jzk5vlFg0Fv60j6W9yBBWjUO9bcVao9nF6CNgQ5OJnC9lelmhSTd9f2_UeDQQfP5A43Ws5uQhl0vub2EFUWKkrt2JdZmM/s400/17.bmp" width="400" /></a></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify; text-indent: 35.4pt;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;"><b style="color: #93c47d;">VI. CONCLUSIONES</b></span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Definiendo un amplificador operacional equilibrado, el cual amplifica tensiones de modo común y de modo diferencial, el análisis y el diseño de circuitos completamente diferenciales puede hacerse de manera simple, de una forma muy similar a las utilizadas habitualmente para trabajar con circuitos </span><i><span style="font-family: Verdana, sans-serif;">single-ended</span></i><span style="font-family: Verdana, sans-serif;">.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">El método propuesto permite analizar y diseñar tanto la respuesta de modo diferencial como la de modo común. Esto permite asegurar la estabilidad del circuito, su respuesta de modo diferencial así también como una dinámica de modo común apropiada.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">A modo de validación, se diseñó y se evaluó experimentalmente un oscilador con salida equilibrada que presenta frecuencias de oscilación de modo común y de modo diferencial independientes entre sí.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><br />
</span> </div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Hernández Caballero Indiana</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Asignatura: CAF</span></span></div><div class="MsoNormal"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif; line-height: 115%;">Fuente:</span> <span style="font-family: Verdana, sans-serif; line-height: 115%;"><a href="http://ewh.ieee.org/reg/9/etrans/ieee/issues/vol5/vol5issue8Dec.2007/5TLA8_01Spinelli.pdf">http://ewh.ieee.org/reg/9/etrans/ieee/issues/vol5/vol5issue8Dec.2007/5TLA8_01Spinelli.pdf</a></span></span></div></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-91451502587334701062010-07-25T23:05:00.002-04:302010-07-27T16:48:00.603-04:30Low power fully differential frequency doubler<div class="post-header"></div><div class="post-body entry-content"><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_filelist.xml" rel="File-List"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_themedata.thmx" rel="themeData"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_colorschememapping.xml" rel="colorSchemeMapping"></link> <style>
<!-- /* Font Definitions */ @font-face {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4; mso-font-charset:0; mso-generic-font-family:roman; mso-font-pitch:variable; mso-font-signature:-1610611985 1107304683 0 0 159 0;} @font-face {font-family:Calibri; panose-1:2 15 5 2 2 2 4 3 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:-1610611985 1073750139 0 0 159 0;} @font-face {font-family:Verdana; panose-1:2 11 6 4 3 5 4 4 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:536871559 0 0 0 415 0;} @font-face {font-family:AdvP2AA1; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 0 0 0 1 0;} @font-face {font-family:AdvP7B6C; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 0 0 0 1 0;} @font-face {font-family:AdvP7B72; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 0 0 0 1 0;} @font-face {font-family:AdvMT_SY; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:auto; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 0 0 0 1 0;} @font-face {font-family:AdvPi1; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 0 0 0 1 0;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {mso-style-unhide:no; mso-style-qformat:yes; mso-style-parent:""; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:0cm; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoPapDefault {mso-style-type:export-only; margin-bottom:10.0pt; line-height:115%;} @page Section1 {size:612.0pt 792.0pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} -->
</style> <br />
<div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span lang="EN-US" style="font-size: small;"> </span> <span lang="EN-US" style="font-size: small;"> </span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span lang="EN-US" style="font-size: small;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;">A novel fully differential frequency doubler is proposed based on CMOS technology, where a stacked push–push configuration is used to generate differential output. Compared to previously reported doublers, the proposed topology has advantages in power dissipation, fundamental frequency rejection, and simplicity. By utilising the proposed doubler, a low power direct-conversion up-mixer is designed for 900 MHz applications. The fabricated up-mixer shows 5.5 dB of power conversion gain and 7.5 dBm of output IP3, while dissipating total current of 4.5 mA from 1.25 V supply.</span><span lang="EN-US" style="font-size: small;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"> </span></div><br />
<div style="text-align: justify;"><div style="text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;"><b style="color: #93c47d;">Introduction: </b>A frequency doubler is a useful component in various RF applications: to avoid VCO injection pulling in direct-conversion transmitters [1], to prevent self-mixing in direct conversion receivers [2], and simply to extend the frequency of oscillation [3]. The important features of the frequency doubler are the conversion efficiency, fundamental frequency rejection, power dissipation, and simplicity as additional circuitry. A few frequency doubler topologies have been reported previously. Kimura and Asazawa [4] reported a frequency doubler based on a dual unbalanced emitter-coupled pair. In this topology, a differential output is obtained for the given differential input. Zhang and Yun [3] reported a push–push frequency doubler based on a differential pair. Zhang and Yun's topology is simple and dissipates half the amount of DC currents than that of Kimura and Asazawa's. However, Zhang and Yun's topology provides only single-ended output for the differential input. The frequency doubler proposed in this Letter dissipates the same current as Zhang and Yun's yet provides fully differential outputs.</span><br />
<br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Proposed frequency doubler: Fig. 1 shows the proposed frequency doubler, which is designed with a stacked push–push configuration using N- and P-MOS transistors to generate differential output. In Fig. 1, the large resistors RB are included for DC biasing which makes no additional DC bias necessary. The output loads at nodes A and B are implemented with inductors considering the low supply voltage of 1.25 V.<br />
<br />
</span> </div></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhguoncDXDp2Mj_sifkXPqlXo3wIgjz_2X1CQKrf-qXkxb2odmIwUoba0v9_sMLUN4c5f6PEbHb8XUMOxFzLH1Dce_0dDGWoT-AiyrdYETMYHojDMxhMmUXAzZicmY91RbjJi-R44P7myY/s1600/1.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="300" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhguoncDXDp2Mj_sifkXPqlXo3wIgjz_2X1CQKrf-qXkxb2odmIwUoba0v9_sMLUN4c5f6PEbHb8XUMOxFzLH1Dce_0dDGWoT-AiyrdYETMYHojDMxhMmUXAzZicmY91RbjJi-R44P7myY/s400/1.bmp" width="400" /></a></div><div style="text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;">In Fig. 1, for the large differential input voltage vin+ and vin-, the transistor pairs M1–M2 and M3–M4 operate as a switch. As shown in Fig. 1, during the first half cycle of the input signal, the transistors M1 and M4 are turned on and M2 and M3 are turned off. The outputs vout+ and vout- follow vin- and vin+, respectively, as M1 and M4 constitute a source follower. Similarly, during the second half cycle of the input signal, the outputs vout + and vout- follow vin+ and vin-. As a result, the frequency of the overall output waveforms, vout+ and vout - , becomes two times that of the fundamental frequency as shown in Fig. 1. With increase in the frequency of operation, the output waveform of the proposed doubler shapes close to the sinusoidal wave. This is due to the limited cutoff frequency of the source follower transistors, yet it has no deteriorating effects on the frequency of interest. The difference in the transconductance of the N- and P-MOS transistors can lead to a mismatch in the amplitude of the two frequency-doubled output signals. This amplitude mismatch can be alleviated by optimising the size of the constituting transistors and the inductances at nodes A and B.</span><span lang="EN-US" style="font-size: small;"></span></div></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;">The performance of the proposed frequency doubler shown in Fig. 1 is evaluated with 450 MHz input signal, which is implemented in 0.25 mm CMOS technology. From the simulation, the frequency doublershows good frequency conversion and -4 dB of gain. In addition, the frequency spectrum of vout+ and vout- shows strong rejection, larger than 50 dB, to the fundamental and other higher odd-order harmonics of the fundamental. The bandwidth of the frequency doubler ideally can approach the cutoff frequency of the transistors as the source follower provides wide bandwidth during each half cycle of the fundamental frequency.</span><span lang="EN-US" style="font-size: small;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Direct-conversion up-mixer: By utilising the newly proposed differential frequency doubler, a direct-conversion up-mixer has been designed as shown in Fig. 2. In Fig. 2, the mixer core is designed based on the Gilbert-cell, and the output load of the mixer is implemented using an external LC network that converts the differential RF output to a single-ended RF signal [2]. The single-ended mixer output helps to reduce the power dissipation of the overall transmitter since it allows a single-ended driver amplifier. In Fig. 2, the output of the frequency doubler is applied directly to the up-mixer core without requiring buffer stages due to the low output impedance of the frequency doubler. The elimination of the buffer stages helps to achieve lower power dissipation.</span></span><span lang="EN-US" style="font-size: small;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"></span><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi9YTebac9QrbOYleL-CHXzsrLeNRDc9Q_TEWP9v8Oj6yNFH9M_7aBU__bOjCcU2K5dVbi2AlfXLLy-W7R1CCmlwmkthQVXGSY9vVDOe_mPLjtg_wVLg42NtxOs1Bc3IG_ttrA1zU9XNlY/s1600/2.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="270" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi9YTebac9QrbOYleL-CHXzsrLeNRDc9Q_TEWP9v8Oj6yNFH9M_7aBU__bOjCcU2K5dVbi2AlfXLLy-W7R1CCmlwmkthQVXGSY9vVDOe_mPLjtg_wVLg42NtxOs1Bc3IG_ttrA1zU9XNlY/s400/2.bmp" width="400" /></a></div><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhhU2FwB6omoP4O2p5z9tJRghOW6tDwQGQewYsC2uuok7TUUYai3_06Lrm6E3bmQCRaPXUs8OeTa_Fx1fWgDWdZQeIzPHAlutHXzHIsfWxWOk28AnNfD3OO2_COEkSNgHXkTokUjN3IA2c/s1600/4.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="310" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhhU2FwB6omoP4O2p5z9tJRghOW6tDwQGQewYsC2uuok7TUUYai3_06Lrm6E3bmQCRaPXUs8OeTa_Fx1fWgDWdZQeIzPHAlutHXzHIsfWxWOk28AnNfD3OO2_COEkSNgHXkTokUjN3IA2c/s320/4.bmp" width="320" /></a></div><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">The direct-conversion up-mixer shown in Fig. 2 has been fabricated based on 0.25 mm CMOS technology. Fig. 3 shows the microphotograph of the fabricated chip. The chip area is 0.5 mm2. In the measurement, 10 MHz IF signal and 450 MHz LO signal are applied to the up-mixer. The measured up-mixer shows 5.5 dB of power conversion gain, 7.5 dBm of output IP3, and 40 dB rejection to the fundamental LO signal, while dissipating 4.5 mA from 1.25 V supply. Of the total current, the frequency doubler dissipates 1 mA. The IP3 behaviour of the designed up-mixer is shown in Fig. 4.</span><span lang="EN-US" style="font-size: small;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiEo32mEVYf7BvHEVNdOmolH5ykjXEKbFaqbJ7JxolD_S9OPZsdbwwokRyS7Fzra5nZJ1dgsoqKUpl2OStiH41QFknVam5DBwMoDJC155iucbZTWM0uwYFVPuBV5-c7-I1K5Mo6oJNMM4c/s1600/3.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="257" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiEo32mEVYf7BvHEVNdOmolH5ykjXEKbFaqbJ7JxolD_S9OPZsdbwwokRyS7Fzra5nZJ1dgsoqKUpl2OStiH41QFknVam5DBwMoDJC155iucbZTWM0uwYFVPuBV5-c7-I1K5Mo6oJNMM4c/s320/3.bmp" width="320" /></a></div><span style="font-size: small;"><br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><div style="text-align: justify;"><span lang="EN-US" style="font-size: small;"><b style="color: #93c47d;">Conclusion:</b> </span><span lang="EN-US" style="font-size: small;">A new fully differential frequency doubler is proposed. The proposed differential frequency doubler provides good conversion gain, high fundamental frequency rejection, and wide bandwidth, yet dissipates half current of the previously reported frequency doubler [4]. By adopting the newly proposed frequency doubler, a low power direct-conversion up-mixer has been designed. The designed up-mixer shows good conversion gain and linearity, and high rejection to the fundamental LO signal.</span></div><div style="text-align: justify;"><br />
</div></div><div class="MsoNormal" style="text-align: justify;"><br />
<div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Hernández Caballero Indiana</span></span></div><span style="font-size: x-small;"></span> <span style="font-size: x-small;"></span> <br />
<div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Asignatura: CAF</span></span></div><span style="font-size: x-small;"></span> <span style="font-size: x-small;"></span> <br />
<div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: x-small;"><span style="font-family: Verdana, sans-serif;">Fuente: </span><span style="font-family: Verdana, sans-serif;"> <a href="http://u-radio.kaist.ac.kr/pdf/journals/2003/9.pdf">http://u-radio.kaist.ac.kr/pdf/journals/2003/9.pdf</a></span></span></div></div></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-89222359952371272072010-06-27T22:10:00.002-04:302010-06-29T18:56:43.445-04:30Nuevos amplificadores operacionales Rail-to-RailLos operacionales EL810x tienen unaúnica alimentación de 5V y están disponibles con o sin un circuito de desactivación de bajo consumo de rápida actuación. El Elantec EL8100 y el EL8101 se caracterizanpor un ancho de banda de 200MHz y un slew rate de 200V/us. El Elantec EL8102 se caracteriza por un ancho de banda de 500MHz y un slew rate de 600V/us. Ofrece ganancia diferencial "best-in-class" de 0.005%. Con una activación de 200ns y desactivación de 13ns, el EL8100 y el EL8102 están especialmente indicados para aplicaciones que requieren multiplexación.<br />
<br />
La última adición a la creciente familia de amplificadores operacionales Elantec de<br />
Intersil ofrece el mayor ancho de banda y slew rate disponible en el mercado a precios muy competitivos. Estos son simplemente los primeros productos en una completa familia rail-to-rail que incluirá operacionales individuales, duales, triples y cuádruples indicados para una amplia gama de aplicaciones de video y de comunicaciones.<br />
<br />
<strong>Ideales para señales de video</strong><br />
Los operacionales Elantec EL810X de Intersil se caracterizan por anchos de<br />
banda de 200MHz y 500MHz, slew rates de hasta 600V/us y consumo de solo 2mA<br />
para el EL8100/01 y 5.6mA para elEL8102. Las salidas rail to-rail oscilan<br />
dentro de 150 mV al rail positivo y 100mV al negativo siendo ideales para amplificaciónde señales de video.<br />
<br />
<strong>Bajo consumo o baja distorsión</strong><br />
<br />
La gama inicial de operacionales individuales incluye dispositivos de 200MHz de<br />
bajo coste y bajo consumo y también dispositivos de 500MHz de gran ancho de<br />
banda y baja distorsión. Indicados para las actuales aplicaciones industriales, video,comunicaciones, e instrumentación que necesitan de muy altas prestaciones y bajo consumo los EL8100/01 están disponibles en encapsulados SO de 8-pines.<br />
<br />
<strong>Características</strong><br />
<br />
• Alimentación de 3V a 5V<br />
• Entrada a 0.1V por debajo de VS<br />
• Salida Rail-to-RailEL8100/8101<br />
• Ancho de banda de 200MHz<br />
• Slew Rate de 200V/μs<br />
• Baja corriente de alimentación= 2mA<br />
• Rápida desactivación de 13ns(sólo EL8100)<br />
<br />
EL8102<br />
<br />
• Ancho de banda de 500MHz<br />
• Slew Rate de 600V/μs<br />
• Baja corriente de alimentación= 5.6mA<br />
• Rápida desactivación de 13ns<br />
<br />
<br />
<strong>Vídeo FrontEnd, 100 MHz,restauración de DC y separador de sincronismos</strong><br />
<br />
<br />
EL EL4501 es un front end de video (VFE) altamente integrado que incorpora todas las funciones básicas de acondicionamiento de señal de vídeo analógico. Proporciona un interface flexible para subsistemas de vido analógico o analógico/<br />
digital.<br />
<br />
El EL4501 tiene una recomposición o restauración de la señal de contínua de gran ancho de banda, un avanzado separador de sincronismos,un separador de señales (data slicer) con umbral ajustable, salida ajustable y modo "powerdown".<br />
<br />
El VFE ofrece restauración de nivel de continua (nivel del blanco ) de señal de vide y recuperación de todos los sincronismos necesarios para el control. Además, los datos integrados en la señal de vídeo o en regiones VBI de vídeo pueden ser extraidos y recuperados utilizando el separador de datos o señales (data slicer) de gran flexibilidad.<br />
<br />
El avanzado separador de sincronismos posee una excelente inmunidad al ruido incorporando un filtro digital y un algoritmo de cualificación de señal. El amplificador de vídeo de continua es estable a ganancia unidad y sin carga en un<br />
ancho de banda de 100 Mhz a –3dBm.<br />
<br />
<br />
<strong>CARACTERÍSTICAS:</strong><br />
<br />
• Separación de sincronismos con recuperación DC<br />
• Recuperación de contínua en un gran ancho de banda (1000 MHz)<br />
• Sepradaro de sincronismos con funciones avanzadas<br />
• Separación de señal-datos programable<br />
• Alimentación simple de 5 Volts.<br />
• ALIMENTACIÓN SIMPLE DE 5 Volts.<br />
• Diff ganancia / fase =0.05 % / 0.03 º, RL=10k ohmios y AV= 1.<br />
• Bajo consumo (< 75 mW ).<br />
<br />
APLICACIONES:<br />
<br />
• Captura de vídeo<br />
• Proyectores de vídeo<br />
• Set top boxes<br />
• Vídeo vigilancia<br />
• Recuperación de señal compuesta<br />
<br />
El rango de tensión de entrada en modo común va desde la alimentación negativa hasta 1.5 voltios de la polarización positiva. Cuando se carga con un coaxial doble de 75 ohmios, el amplificador puede entregar señal hasta 150 mV dentro de la alimentación. Con 2000 V/micro seg de slew rate, el amplificador es el ideal para aplicaciones de vídeo compuesto.<br />
<br />
El VFE funciona con alimentación simple de 5 voltios y en rango de temp. De –40ºC a +85ºC, y está disponible en encapsulado de 24 pines QSOP.<br />
<br />
<strong>Separador de Sincronismos de Vídeo compatible con dos y tres niveles para DTV,<br />
HDTV y Proyectores</strong><br />
<br />
<br />
El separador de sincronismos de Vídeo EL4511, está diseñado para dispositivos de nueva generación DTV,HDTV y proyectores así como también para equipamientos de transmisión y otras aplicaciones que requieran procesamiento de señal de vídeo.<br />
<br />
El EL4511 soporta automáticamente sincronismo sobre verde, sincronismo separado, y entradas H/V síncronas seleccionando el tipo de formato. También es capaz de detectar y decodificar tres niveles de sincronismo utilizados en los últimos sistemas de almacenamiento.<br />
<br />
Por encima de un Separador de sincronismos estándar,el EL4511 puede detectar automáticamente la velocidad de línea y bloquearla, sin utilizar la resistencia<br />
externa RSET. El EL4511 esta disponible en un encapsulado QSOP de 24 pines y opera en un rango de temperatura de 0 a 85ºC.<br />
<br />
Características<br />
<br />
• Compatible con composite, component, HDTV y señal de PC<br />
• Compatible con sincronización de dos y tres niveles<br />
• Detección automática de sincronización<br />
• 200 Khz max line rate<br />
• Opciones de encapsulado pequeño<br />
• Rango de tensión de entrada de 3.3 a 5V<br />
<br />
Aplicaciones<br />
<br />
• Entradas analógicas HDTV/DTV.<br />
• Video proyectores.<br />
• Monitores de ordenador.<br />
• Set top boxes.<br />
• Sistemas de seguridad por vídeo.<br />
• Equipos de transmisión de vídeo.<br />
<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_EIyD6JwuvgUDmfTDjvKl7xvcsj6grD9fgeFFNGt0gWd57QXoRUJzxUIe2rIyrYUeMZHw-4jStvTcoW82j2dxxu0kSAyyllkzncr3gLS-1dgaVKgpuEJ-0xOBnavIrdJ7sXUBR3ZzH4mf/s1600/1.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487583555885329170" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_EIyD6JwuvgUDmfTDjvKl7xvcsj6grD9fgeFFNGt0gWd57QXoRUJzxUIe2rIyrYUeMZHw-4jStvTcoW82j2dxxu0kSAyyllkzncr3gLS-1dgaVKgpuEJ-0xOBnavIrdJ7sXUBR3ZzH4mf/s320/1.JPG" style="cursor: hand; height: 224px; width: 320px;" /></a><br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjeaJ5_ZR2MUXsNY2QzVSYeBlNiMHOnt30H6L7HQGaT5TWPTYv1M_1Si6w6PIg3Q1kJ_Vezd30ErElYL_Nm3giPCS3YOHP_kLMAL4jJVcvgCxpyegYvnAUT6yPTWF5ALot7YVcHWPWT0jrG/s1600/2.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487583915137081954" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjeaJ5_ZR2MUXsNY2QzVSYeBlNiMHOnt30H6L7HQGaT5TWPTYv1M_1Si6w6PIg3Q1kJ_Vezd30ErElYL_Nm3giPCS3YOHP_kLMAL4jJVcvgCxpyegYvnAUT6yPTWF5ALot7YVcHWPWT0jrG/s320/2.JPG" style="cursor: hand; height: 224px; width: 320px;" /></a><br />
<br />
Nombre Alexander sayago<br />
C.I 16232455 <br />
Seccion 1 Materia Estado SolidoTecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-18163826930856609742010-06-27T22:09:00.002-04:302010-06-29T18:56:24.940-04:30Las aplicaciones emergentes conducen los avances en los amplificadoresLas exigencias actuales sobre el funcionamiento de los sistemas en una gama variada de aplicaciones requieren a un número cada vez mayor de ingenieros, la capacidad de elegir y diseñar con amplificadores de bajo ruido en los que se incluyen amplificadores operacionales, preamplificadores de audio y amplificadores de instrumentación. Comprender los parámetros clave que ayudan a los diseñadores de circuitos integrados (CI) a mejorar el rendimiento del ruido podría ayudar a los ingenieros a obtener soluciones eficaces.<br />
<br />
<strong>Exigencias de un público cada vez más numeroso</strong><br />
<br />
Diseñar con amplificadores de bajo ruido ha sido principalmente dominio exclusivo de la fraternidad de las microondas y de la RF. Pero muchos tipos de equipos electrónicos de uso habitual requieren ahora gestionar señales de amplitud ultra-baja, a altas resoluciones y con niveles bajos de distorsión. Ejemplos de ello son los equipos profesionales de audio, los instrumentos de monitorización ambiental, los controles industriales y los sistemas de formación de imágenes médicas; y los diseñadores deben comprender con rapidez cómo obtener un funcionamiento de bajo ruido. La selección correcta del dispositivo es crítica si el sistema resultante tiene que satisfacer sus objetivos de funcionamiento.<br />
<br />
Cuando se evalúa un circuito integrado de un amplificador para una aplicación de bajo ruido, los dos factores más importantes a considerar son el ruido de tensión y el ruido de corriente. Estos aspectos "no ideales" del comportamiento de un amplificador operacional se pueden modelar como fuente de ruido de tensión en serie con un terminal de entrada de un amplificador operacional ideal que no produzca ruido, y dos fuentes de ruido de corriente entre cada terminal de entrada y común. Se puede considerar normalmente que estas fuentes son independientes entre sí. <br />
<br />
Cuando se describe el ruido de la corriente y el ruido de la tensión en la hoja de datos de un amplificador operacional, las cifras indicadas están normalmente referenciadas a la entrada del dispositivo, para eliminar cualquier dependencia de la ganancia.<br />
<br />
En el esquema de la figura 1, el ruido instantáneo combinado en la salida del amplificador se puede considerar como la suma de los efectos de dos tipos de ruido:<br />
eo = (1+ R2/R1) x en + R2 x ruido de la corriente de E/S<br />
<br />
<br />
Donde:<br />
eo=ruido instantáneo combinado de salida<br />
<br />
en = ruido de tensión<br />
in = ruido de corriente<br />
<br />
De esta ecuación, se puede calcular la contribución relativa de cada tipo de ruido como:<br />
<br />
en/in = R2 / (1+ R2/R1)<br />
<br />
Por consiguiente, la fuente de ruido dominante puede variar según la impedancia de entrada del circuito. El ruido de tensión domina en los circuitos de impedancia de generador baja, mientras que el ruido de corriente se hace cada vez más importante en los valores más altos de impedancia del generador. Esto tiene una influencia importante sobre la selección del amplificador. En las aplicaciones en que la impedancia del generador es baja, los diseñadores deberán seleccionar un amplificador operacional que ofrezca un ruido de tensión bajo. Para aquellas aplicaciones con generadores de impedancia alta, es preferible un amplificador con bajo ruido de corriente de entrada. La relación entre en y in (utilizando los valores RMS) se conoce como la Resistencia Característica del Ruido, que puede ser una cifra digna de considerar para evaluar la capacidad funcional de un amplificador en relación con la impedancia de cualquier generador previsto.<br />
<br />
También es de gran valor tener en cuenta que tanto el ruido de tensión como el ruido de corriente varían sobre la anchura de banda de un amplificador operacional. Los diseñadores necesitan por lo tanto prever el valor de cada uno a la frecuencia prevista de funcionamiento para confirmar que el dispositivo elegido funcione según lo previsto en la aplicación final. Se puede obtener la información adecuada de la hoja de datos, o bien, hallarla por experimentación.<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgLnVPRuGPjap3w_LHpuyjdIrQx2tkd31es5bBJG9H2iFLDCpFRbWVynrLFrKc3ydyt_Ix30MFb0RYUF7B2XW3R678n4FE8CjX4OX6zk6BPbNRAVwUI1p6We28t2HcGw7vCCMVFiJxt5Fz2/s1600/25.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487569519205770514" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgLnVPRuGPjap3w_LHpuyjdIrQx2tkd31es5bBJG9H2iFLDCpFRbWVynrLFrKc3ydyt_Ix30MFb0RYUF7B2XW3R678n4FE8CjX4OX6zk6BPbNRAVwUI1p6We28t2HcGw7vCCMVFiJxt5Fz2/s320/25.JPG" style="cursor: hand; height: 224px; width: 320px;" /></a><br />
<br />
Figura 1 Fuentes de ruido debido a la tensión y a la corriente en una red de amplificador.<br />
<br />
<strong>Criterios fundamentales de selección del dispositivo</strong><br />
<br />
Los amplificadores de bajo ruido actualmente disponibles están fabricados con la tecnología bipolar, de JFET o del proceso CMOS. En la tecnología bipolar, el ruido de la tensión es inversamente proporcional a la raíz cuadrada de la corriente del colector de la etapa de entrada. Los diseñadores del chip, pueden por lo tanto obtener un rendimiento de ruido de tensión bajo aumentando este valor de la corriente. Consecuentemente, cuando se comparan los amplificadores de tecnología bipolar con los de las tecnologías JFET o CMOS, los de tecnología bipolar tienden a producir la densidad más baja de ruido de tensión. Para los amplificadores operacionales bipolares de bajo ruido, esta densidad puede ser normalmente de alrededor de 1-2nv/√Hz. Sin embargo, el ruido de la corriente es directamente proporcional a la raíz cuadrada de la corriente del colector y, consecuentemente, es relativamente alto cuando el ruido de la tensión es bajo. De aquí que la realimentación externa y la resistencia del generador deban mantenerse bajas para garantizar un buen rendimiento del ruido. Las aplicaciones más adecuadas para los amplificadores bipolares, por lo tanto, son aquellas que tienen una impedancia de entrada baja, normalmente inferior a 200 Ω.<br />
<br />
Inversamente, los amplificadores con etapas de entrada JFET muestran una densidad de ruido de corriente sumamente baja, normalmente de menos de 1fA/√Hz. Esto resulta en una corriente de polarización muy baja, lo cual hace que estos dispositivos sean adecuados para aplicaciones con impedancia del generador muy alta. Por otro lado, la densidad del ruido de la tensión tiende a ser de un orden de magnitud más alta que la del dispositivo bipolar, lo que impone una reducción del rendimiento en aplicaciones con impedancia del generador muy baja. Los amplificadores JFET pueden además operar de una alimentación simple, lo cual puede facilitar el diseño del suministro de energía.<br />
<br />
Los amplificadores CMOS ofrecen buen rendimiento general contra el ruido, comparable con el rendimiento del ruido de tensión de los dispositivos bipolares, y asimismo con el rendimiento del ruido de corriente de los dispositivos de entrada JFET. Otros beneficios incluyen la baja distorsión y su operación de una alimentación simple, lo cual les hace adecuados para aplicaciones tan diversas como la amplificación de señales de sensores o de preamplificadores de audio.<br />
<br />
<strong>Mejoras en los niveles de ruido</strong><br />
Pero el orden establecido está cambiando; las exigencias cada vez mayores de un funcionamiento de bajo ruido en el diseño de los aparatos electrónicos de uso general está forzando la aparición de nuevas generaciones de circuitos integrados para amplificadores de bajo ruido que ofrecen mejor rendimiento general. Históricamente, la creación de un amplificador de bajo ruido hacía necesario que los diseñadores de circuitos integrados intercambiaran otros aspectos del funcionamiento como la velocidad, la corriente de polarización de entrada y el consumo de la energía. El tamaño del dado y de la cápsula de los dispositivos de bajo ruido tienden también a ser mayores que los de los amplificadores de uso general. En las aplicaciones de bajo ruido tradicionales, como en las comunicaciones por satélite, radar o GSM inalámbrico, tales inconveniencias han sido secundarias a la importancia de obtener el rendimiento de ruido requerido. Sin embargo, con las realidades comerciales modernas frecuentes en las últimas generaciones de aplicaciones de bajo ruido, surgen requisitos necesarios de bajo ruido de tensión y de bajo ruido de corriente, además de baja energía, precio económico y pequeño tamaño.<br />
<br />
Otras exigencias importantes que afectan a los sistemas modernos incluyen el soporte de la oscilación de la tensión de entrada o salida de un carril a otro, para potenciar al máximo el rango dinámico de la señal ya que los amplificadores deben operar a partir de unas tensiones de alimentación del sistema progresivamente inferiores. Otros requisitos incluyen el rechazo de la alimentación de alta potencia, por ejemplo en los productos diseñados para operar a partir de una tensión de batería no regulada. Estos deben también operar sobre la gama total de tensión útil de la batería, ya que la tensión de alimentación decae progresivamente del nivel totalmente cargado. Satisfacer todos estos requisitos en un solo amplificador es un reto.<br />
<br />
Las innovaciones del proceso en las tecnologías bipolar, JFET y CMOS han posibilitado nuevas familias de dispositivos que muestran propiedades muy optimizadas. Un ejemplo:Telecomunicacioneslos amplificadores bipolares líderes están adoptando una nueva tecnología de aislamiento por zanja en lugar de la estructura tradicional de capa de difusión para obtener una densidad de transistor mayor por dado. Esta tecnología ofrece mayor velocidad, adaptación, linealidad y estabilidad, además de reducir el ruido producido por la tensión y la corriente. Los beneficios incluyen menor consumo de energía, operar sobre una gama extendida de temperaturas sin que se requieran disipadores térmicos, y que los encapsualdos sean más pequeños, con lo cual se pueden obtener densidades mayores en los diseños de canal múltiple.<br />
<br />
Los avances en la tecnología de fabricación JFET incluyen la construcción de transistores multipuerta para el rendimiento óptimo por área de transistor, lo cual ha permitido reducir el ruido de la tensión manteniendo simultaneamente un ruido de corriente ultra bajo. Con un ruido de tensión en el rango de 4-6nV/√Hz y un ruido de corriente de menos de 1fA/√Hz, los dispositivos de la última generación han obtenido un ruido total bajo sobre una amplia gama de impedancia de transductor. Presentan una solución especialmente robusta cuando se tratan de amplificar señales de bajo nivel procedentes de generadores de impedancia alta, especialmente de transductores capacitivos, como los hidrófonos, los acelerómetros de precisión o los fotodiodos.<br />
<br />
El desarrollo del amplificador CMOS se está también enfocando en los avances en el nivel de silicio para eliminar los compromisos entre aspectos tales como baja derivación y bajo ruido, que también han sido difíciles de combinar en un sólo dispositivo. Otros avances de procesos incluyen el silicio con aislador (SOI) BiCMOS, que ofrece una precisión mejorada de CC, un bajo consumo de la energía y bajo ruido de tensión. Diseñados para tensiones de alimentación de 0,9V-12V, que incluye la optimización para una operación de 3,3V-5V, permiten la interconexión directa al convertidor A/D además de la compatibilidad con la química de la batería, como las de ión de Li, haciendo que sean muy adecuados para utilizar en los dispositivos portátiles.<br />
<br />
Nombre Alexander Sayago <br />
C.I:16232455<br />
Seccion 1 Materia Estado SolidoTecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-34360169279307113312010-06-27T22:07:00.002-04:302010-06-29T18:56:03.595-04:30Limitaciones de Amplificadores Operacionales<strong>Saturacion<br />
</strong>La salida maxima del amplificador es aproximadamente 80%−90% del voltaje de las fuentes de potencia (mas o menos ±13V si las fuentes son ±15V ) a menos que sean del tipo "railto-rail". Estos ultimos pueden alcanzar voltajes muy cercanos a los de la fuente de potencia.En cualquier caso, la salida sufrira recorte una vez alcance el voltaje de saturacion en el lado positivo o negativo.<br />
<br />
<strong>Corriente de corto circuito</strong><br />
<br />
El AO tiene un circuito de proteccion que limita la corriente a un valor maximo, llamado la corriente de corto circuito (short-circuit current, SCC). Si la corriente de salida que el AO suple o absorbe alcanza este valor, la magnitud el voltaje de salida deja de aumentar,limitando ası la corriente al valor de este parametro.<br />
<br />
Ejemplo: Determine las resistencias mas pequeña que puede ser usada en un amplificador sin inversion sencillo con ganancia de 4V/V de tal modo que no se supere la corriente de corto circuito ISCC = 20mA cuando vO = 14V . El amplificador tiene una carga RL = 1kΩ conectada a la salida.<br />
<br />
<strong>Disipacion de potencia</strong><br />
La operacion del AO requiere la extraccion de una cantidad de corriente IQ (llamada el quescient current en ingles), aun cuando la salida se mantenga en cero.Si vO=0V, el AO disipa internamente una potencia igual a<br />
<br />
P = (VCC + VEE)IQ<br />
<br />
donde VCC y −VEE representan los voltajes positivo y negativo de la fuente de potencia,respectivamente. Valores tipicos son VCC = +15V y −VEE = −15V .<br />
Si la salida no es cero, una corriente iO debe ser provista a la carga y a la red de retroalimentacion. La misma debe ser extra´ıda de la fuente de potencia en adici´on a IQ. Esta corriente entrar´a o saldr´a del AO dependiendo de la polaridad de vO.<br />
Si vO > 0, iO sale del AO y la corriente de la fuente VCC se convierte en IQ + iO. La<br />
potencia disipada internamente es<br />
<br />
P = (VCC + VEE)IQ + (VCC − vO)iO<br />
<br />
Si vO < 0, iO entra al AO y la corriente de la fuente VEE se convierte en IQ + iO. La<br />
potencia disipada internamente es<br />
<br />
P = (VCC + VEE)IQ + (vO + VEE)iO<br />
<br />
Note que los voltajes del power supply son VCC y −VEE (o sea, VEE es un voltaje positivo).<br />
Ejemplo: Determine la potencia disipada por el AO usado en el ejemplo anterior si <br />
vO =14V e IQ = 1mA. Use VCC = VEE = 15V .<br />
<br />
<strong>Ancho de banda</strong><br />
<br />
La mayorıa de los AO son compensados internamente para hacerlos incondicionalmente<br />
estables. Esto significa que el circuito interno contiene componentes que hacen que exista un polo dominante que se encuentra a una frecuencia mucho mas baja que los demas polos.<br />
<br />
Esta situacion se muestra en la siguiente figura:<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgw1xTzB_4I3v2Kn_NS9xcKw03hzb10oLbKzN0B39v88_ybWrvnG3TNTwHX3l7rLkm6zMFJInROIk5JMgkVtZ-zXvtWwCU0mv4_GbjcidKTAsKe1m7ZNucx98J3zYMqmG9M8VUTA3E0Qk1H/s1600/1.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487301431033528418" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgw1xTzB_4I3v2Kn_NS9xcKw03hzb10oLbKzN0B39v88_ybWrvnG3TNTwHX3l7rLkm6zMFJInROIk5JMgkVtZ-zXvtWwCU0mv4_GbjcidKTAsKe1m7ZNucx98J3zYMqmG9M8VUTA3E0Qk1H/s320/1.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
El diagrama muestra las siguientes cantidades: la ganancia de lazo abierto a, la ganancia de lazo cerrado del amplificador sin inversion 1+ R2/R1<br />
y la frecuencia de ganancia unitaria fτ .<br />
<br />
Este tipo de aparato se conoce como amplificador con producto ganancia-ancho de banda(GBP) constante. Como indica el termino, la reduccion en la ganancia del amplificador(causada por el uso de retro-alimentacion negativa) esta acompañada de un aumento similar en el ancho de banda, el cual puede ser calculado usando la formula<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiet0hkxzXui8DtsPspa3XoQcrkXCRST2K73BugXNbU0XZC1Um_CW3kshrLRTj8u63sZBjKQoL0iYtJlyIm6F4FSLjYFXe85FWsXLO9Ew1Ps8B2gG-_oygwooiY6tmZvCJHkMw534zAUr6r/s1600/2.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487302419932617810" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiet0hkxzXui8DtsPspa3XoQcrkXCRST2K73BugXNbU0XZC1Um_CW3kshrLRTj8u63sZBjKQoL0iYtJlyIm6F4FSLjYFXe85FWsXLO9Ew1Ps8B2gG-_oygwooiY6tmZvCJHkMw534zAUr6r/s320/2.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
Ejemplo: Calcule el ancho de banda de un amplificador con ganancia A = +100V/V y<br />
que utiliza el AO μA741 con fτ = 1MHz.<br />
<br />
Amplificador con n etapas identicas<br />
<br />
Si se desea un GBP mas grande, se pueden usar varias etapas para obtener un amplificador con la misma ganancia total. En el ejemplo anterior, la ganancia de <br />
+100V/V se puede obtener con dos etapas con ganancia de +10V/V.Sin embargo, en este caso el ancho de banda global no es igual al de cada etapa, pues a la frecuencia fbw cada etapa reduce la ganancia por 3dB y la atenuacion total es 6dB.<br />
<br />
Podemos obtener una formula para determinar el ancho de banda de un amplificador con n etapas identicas partiendo de la respuesta de frecuencia de cada etapa,<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjOUGHyJ43wB1fBT2Wy6RAm804TI0qel0m20YlyTavDTBK-_3muZDG3hE_HOhsh-7YVw6S-9JMuL2U4e9ffUlhDZcTLQZPGOXIctcYudsBx6pByd-oQFAvHxblxCDC6yPcrFNTWptGjW2J3/s1600/3.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487303451972706658" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjOUGHyJ43wB1fBT2Wy6RAm804TI0qel0m20YlyTavDTBK-_3muZDG3hE_HOhsh-7YVw6S-9JMuL2U4e9ffUlhDZcTLQZPGOXIctcYudsBx6pByd-oQFAvHxblxCDC6yPcrFNTWptGjW2J3/s320/3.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
Para n etapas la ganancia total es<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgV6NxOKup173ZBdsDiP-3zO30iq0Y7gvI3vDjES6pv1MRGXHPaNh34p2vTcmc37vsW2CpWCnijCYxPpxt8-M2vM2Xxw5XzrvR9qCWZGUfhDm_SYyUdrfR8rJEwRFGs_Yej83ICO3nYImud/s1600/4.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487303830385027602" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgV6NxOKup173ZBdsDiP-3zO30iq0Y7gvI3vDjES6pv1MRGXHPaNh34p2vTcmc37vsW2CpWCnijCYxPpxt8-M2vM2Xxw5XzrvR9qCWZGUfhDm_SYyUdrfR8rJEwRFGs_Yej83ICO3nYImud/s320/4.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
donde An0i = A0, la ganancia d.c. deseada. Notando que<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEggz2Fn7MCKTZAzA7MDphxKWRw1nfm1SkvJpMPhY1hlqphJu4lv4qnNJj72Igq8-xyQXtMmg_TZzaSpqDdWQ6KpA1_0cBj8imipd98xy_zejs5H1fFWomzuoMO3h1tyzjIeRRuB5JyFPJ-n/s1600/5.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487304755007802402" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEggz2Fn7MCKTZAzA7MDphxKWRw1nfm1SkvJpMPhY1hlqphJu4lv4qnNJj72Igq8-xyQXtMmg_TZzaSpqDdWQ6KpA1_0cBj8imipd98xy_zejs5H1fFWomzuoMO3h1tyzjIeRRuB5JyFPJ-n/s320/5.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
<br />
y que a la frecuencia fBW (el ancho de banda del amplificador de n etapas) la ganancia totales igual a A0/√2, tenemos que<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjDYiTeVZBxmNUvAyWqfqkWNpi4UiAXsGy5qQF8c6RAXUBJcOq6645s-P1LoFbuGkrERNAgPG7oytp3AdV3QB3MMea-GMbDDgaUELNbMv926Vgpjod6wxTRHzw6fdmaGRern60ZZL7ubZtZ/s1600/6.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487305153212248050" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjDYiTeVZBxmNUvAyWqfqkWNpi4UiAXsGy5qQF8c6RAXUBJcOq6645s-P1LoFbuGkrERNAgPG7oytp3AdV3QB3MMea-GMbDDgaUELNbMv926Vgpjod6wxTRHzw6fdmaGRern60ZZL7ubZtZ/s320/6.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
y<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgVD592JbhczL4UenLRF36kecTdbUzVML9LzhkLLGXtC3EW6lXvaJhW2caSf2dcAjcNrtxGlsigFlCi8scuC_aznZ9mhkaQGrKi28hkXuKosiBtI0hG77E9GVJVt9dz1c73PE932QF8HSyo/s1600/7.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487305510768782722" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgVD592JbhczL4UenLRF36kecTdbUzVML9LzhkLLGXtC3EW6lXvaJhW2caSf2dcAjcNrtxGlsigFlCi8scuC_aznZ9mhkaQGrKi28hkXuKosiBtI0hG77E9GVJVt9dz1c73PE932QF8HSyo/s320/7.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
<br />
<br />
donde fBW es el ancho de banda del amplificador de n etapas, A0 es la ganancia del amplificador de n etapas, y n√A0 es la ganancia de cada etapa.<br />
<br />
Ejemplo: Determine el ancho de banda de un amplificador con A = 500V/V si se usan<br />
(i) una etapa, (ii) dos etapas, y (iii) tres etapas sin inversion. Asuma que se utiliza el AO μA741.<br />
<br />
Etapas con inversion<br />
La descripcion anterior se refiere a n etapas sin inversion. Si se utilizan etapas con inversion, el ancho de banda debe calcularse usando 1 + R2/R1 aunque la ganancia de cada etapa es −R2/R1. Las formulas aplican sin modificacion pero el GBP es inferior.<br />
<br />
Ejemplo: Determine el ancho de banda de un amplificador si se usan (i) una etapa, (ii) dos etapas, y (iii) tres etapas con inversi´on para obtener una ganancia total con magnitud igual a 500V/V . Asuma que se utiliza el AO μA741.<br />
<br />
<strong>Razon de cambio maxima (Slew-rate)</strong><br />
<br />
La respuesta de escalon de un amplificador de GBP constante debe ser<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjWsHYIMhlK3aBF9zhbY8epZxpWW1u-nNdoJC_Xi0XZVfgYe1YoWGU9fJlfOJq6AqwxyZaLIdsVbhkExWyhgx_f-N_tXI0nMW6JIW9SDyX1_jq2kNi6n_FWx_jfFZRWB8BLF3szxRIRSz9j/s1600/8.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487309225534048610" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjWsHYIMhlK3aBF9zhbY8epZxpWW1u-nNdoJC_Xi0XZVfgYe1YoWGU9fJlfOJq6AqwxyZaLIdsVbhkExWyhgx_f-N_tXI0nMW6JIW9SDyX1_jq2kNi6n_FWx_jfFZRWB8BLF3szxRIRSz9j/s320/8.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
pues actua como un sistema de primer orden. En esta expresion τ = 1/2πfbw. Sin embargo,debido a limitaciones del circuito interno del AO, si el escalon supera un tamaño particular,una respuesta de pendiente constante precedera a la respuesta exponencial, tal como muestra en la siguiente figura.<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg0zt_ZcXXiP6uoQGldVsttIHTyT2AzaDuy9kpoPKqjFcMV3dQmakplpU879K9jHoP-_96Skb3eDsRBZI6o_LvfBxFV47f-A_esoG_Rnk6Hc7LNH1atyqul8xlMa00eU9mUio8wl1Vx0cky/s1600/9.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487310328813877698" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg0zt_ZcXXiP6uoQGldVsttIHTyT2AzaDuy9kpoPKqjFcMV3dQmakplpU879K9jHoP-_96Skb3eDsRBZI6o_LvfBxFV47f-A_esoG_Rnk6Hc7LNH1atyqul8xlMa00eU9mUio8wl1Vx0cky/s320/9.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
La razon maxima a la que puede cambiar el voltaje de salida se conoce comoslew-rate<br />
(SR). Si la señal requiere un cambio mas rapido,la señal se distorsiona y la razon de cambio se limita al slew-rate. Ejemplos de señales limitadas de este modo son los siguientes:<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjy3m3158pJ9r-mV0b4TVRKPm9DVLC3MS8sPf3D-Re_X5FClGomoq7HrkWjLG8wx1WK67pkfXdCpuYtIDDs0nbFASyBouVzRhcLO0wYUK9xIAI1R-w9HFVbat6ipWg9q3SfFdHEz6vu0gOh/s1600/10.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487311099501755618" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjy3m3158pJ9r-mV0b4TVRKPm9DVLC3MS8sPf3D-Re_X5FClGomoq7HrkWjLG8wx1WK67pkfXdCpuYtIDDs0nbFASyBouVzRhcLO0wYUK9xIAI1R-w9HFVbat6ipWg9q3SfFdHEz6vu0gOh/s320/10.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
<br />
Para determinar el tamaño maximo del escalon que sera libre de este tipo de distorsion,observe que<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh05fXbjAbsM6Pmd0tvOEJVJPzX6GKWTScXW__OWfz3egfUiXME-04q9e0VgpMcvFgzFNrsbVaLiK75C2fmQjJ8nJOIaOwfZn83XcdtnCUcSKukKiGO1pS3BnzyMz_-r81M9el4_QtC22sq/s1600/11.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487311806023210674" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh05fXbjAbsM6Pmd0tvOEJVJPzX6GKWTScXW__OWfz3egfUiXME-04q9e0VgpMcvFgzFNrsbVaLiK75C2fmQjJ8nJOIaOwfZn83XcdtnCUcSKukKiGO1pS3BnzyMz_-r81M9el4_QtC22sq/s320/11.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
<br />
es maximo en t = 0. Por tanto, si<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg3uJys37LXqcuXYy8JzGUm0wrv1cCf7fYwqWhwgcP2PmJl4HarlH7ueytl6xlqYc38RyaJmeLvao3jT5ROYq4EtNxQRs-S1bW7sDCi7zBrZnBUfbFLWGgnqmT_EILl2HLZc-KOcQZMuhZ5/s1600/12.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487312472968961314" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg3uJys37LXqcuXYy8JzGUm0wrv1cCf7fYwqWhwgcP2PmJl4HarlH7ueytl6xlqYc38RyaJmeLvao3jT5ROYq4EtNxQRs-S1bW7sDCi7zBrZnBUfbFLWGgnqmT_EILl2HLZc-KOcQZMuhZ5/s320/12.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
la salida no sera limitada por el SR. Esta formula se puede expresar como<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgUDklb8V6fimJRTKyKPWaWcFL5c4oWIP1ARraccBT_4Q7h37RbUIIfaa2gqBI3AZxlFV-z79lBU-44rd6DCpkNAjgCKttQKFs3PEEIn3evwun_WUfhd4B5O23xXP2sWxym7loDPn3waNJf/s1600/13.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487313177259430002" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgUDklb8V6fimJRTKyKPWaWcFL5c4oWIP1ARraccBT_4Q7h37RbUIIfaa2gqBI3AZxlFV-z79lBU-44rd6DCpkNAjgCKttQKFs3PEEIn3evwun_WUfhd4B5O23xXP2sWxym7loDPn3waNJf/s320/13.JPG" style="cursor: hand; height: 215px; width: 320px;" /></a><br />
<br />
donde Vm representa el tamaño del escalon en la salida del amplificador y fbw es el ancho de banda del amplificador.<br />
En el case de una se˜nal senoidal de frecuencia f,<br />
<br />
v(t) = Vm sin (2πft)<br />
<br />
la razon de cambio es<br />
<br />
dv(t)/dt = 2πfVm cos (2πft)<br />
<br />
y tambien es maxima en t = 0 asi que para tener una señal libre de distorsion,<br />
<br />
2πfVm ≤ SR<br />
<br />
Esta condicion se puede expresar como<br />
<br />
f ≤ SR/2πVm<br />
<br />
o como<br />
<br />
Vm ≤ SR/2πf<br />
<br />
Ejemplo: Calcule fmax si Vm = 10V y SR = 0.5V/μs.<br />
<br />
<strong>Corrientes de polarizacion</strong><br />
<br />
El funcionamiento de AO que utilizan transistores bipolares requiere que exista corriente en los terminales de entrada del aparato. La corriente de polarizacion o bias current se define como el promedio de la corriente que entra o sale de los terminales<br />
<br />
IB =Ip + In/2<br />
<br />
La diferencia entre las corrientes que entran a los terminales se llama corriente de offset y se define como<br />
<br />
IOS =| Ip − In |<br />
<br />
Debido a que es causada por errores aleatorios en la fabricacion del circuito integrado, no es posible conocer el signo de IOS de antemano. Tıpicamente, IOS es un orden de magnitud menor que IB.<br />
<br />
La tabla 1 muestra valores2 de IB e IOS para varios AO de uso comun. Puede observarse<br />
la amplia de valores que pueden obtenerse de los distintos aparatos.<br />
<br />
Table 1: Parametros de Varios AO<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiSUJnjTPVrFiMTpHpUh287PHUaqZ0cRcbkNC5j9VmgNKVm3y_DG2113rF_dstEiPXYUosp1VNHl0JS66c2bmLNPadVFNadDSYd788GAGQw5PDv7psY1782Y-80DFNzeQ7PfKRjYE09gL6T/s1600/11.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487556408153121426" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiSUJnjTPVrFiMTpHpUh287PHUaqZ0cRcbkNC5j9VmgNKVm3y_DG2113rF_dstEiPXYUosp1VNHl0JS66c2bmLNPadVFNadDSYd788GAGQw5PDv7psY1782Y-80DFNzeQ7PfKRjYE09gL6T/s320/11.JPG" style="cursor: hand; height: 243px; width: 320px;" /></a><br />
<br />
<br />
<br />
La tabla 1 muestra valores2 de IB e IOS para varios AO de uso comun. Puede observarse<br />
la amplia de valores que pueden obtenerse de los distintos aparatos.<br />
<br />
En adicion al valor de IB especificado en la tabla, es importante considerar las variaciones del parametro con temperatura. La misma puede resumirse como sigue:<br />
• en AO que utilizan transistores bipolares, la IB disminuye a medida que la temperatura aumenta, debido a que la β de los transistores aumenta con T;<br />
<br />
• en AO construidos con JFETs, IB se duplica cada vez que la temperatura aumenta<br />
por 10◦C, segun la formula <br />
<br />
IB(T) = IB(T0) × 2(T−T0)/10<br />
<br />
• en circuitos basados en MOSFETs, la dependencia es similar a aquellos basados en<br />
JFETs debido a la presencia de diodos usados para protecci´on contra descargas de<br />
electricidad estatica.<br />
<br />
<strong>Error debido a IB</strong><br />
<br />
Considere el siguiente diagrama,<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEit9xvcn77k-sLfWC9fELGbPgUQw-_da6lDViVbWbOoxOydCRUrhWk6wD5uH1J1d0KECBZD6ojKR7T9hu_ImspJWmzxXrm6lp7EIe5S2HoV6lChATzm1DAw_xQE6uuPn_Kp4TAxFU5QhRno/s1600/12.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487557977927486242" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEit9xvcn77k-sLfWC9fELGbPgUQw-_da6lDViVbWbOoxOydCRUrhWk6wD5uH1J1d0KECBZD6ojKR7T9hu_ImspJWmzxXrm6lp7EIe5S2HoV6lChATzm1DAw_xQE6uuPn_Kp4TAxFU5QhRno/s320/12.JPG" style="cursor: hand; height: 243px; width: 320px;" /></a><br />
<br />
donde por conveniencia las corrientes de polarizacion se representan como fuentes externas a un AO ideal. Los terminales de entrada estan virtualmente conectados, y<br />
<br />
vn = vp = −IpRx<br />
<br />
IR1 = −(Rx/R1)*Ip<br />
<br />
El error causado por las corrientes es<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiEaWR8D7JD9VEI_BHdnHbowJhvWrUlAPumjh1WoyP1k9NdThRHUt07OVXIKJBQ6T-8xDNidd0yQ9z8sMX9omv1vLtkr3B0hE81QIb6g4z_p-eboOSbAn61xLHzEza-u2NtnY0uP0d1FRHI/s1600/13.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487558599812653826" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiEaWR8D7JD9VEI_BHdnHbowJhvWrUlAPumjh1WoyP1k9NdThRHUt07OVXIKJBQ6T-8xDNidd0yQ9z8sMX9omv1vLtkr3B0hE81QIb6g4z_p-eboOSbAn61xLHzEza-u2NtnY0uP0d1FRHI/s320/13.JPG" style="cursor: hand; height: 243px; width: 320px;" /></a><br />
<br />
<br />
Para reducir este error, podemos (i) reducir el tamaño de R2 (y consecuentemente el de R1 para mantener la misma ganancia), o (ii) escoger<br />
<br />
Rx = R1 || R2<br />
<br />
de tal modo que el error debido a IB, que usualmente es el componente mas importante, se cancele. En tal caso, el error restante es<br />
<br />
EO = ±IOSR2<br />
<br />
donde se a incluido la incertidumbre en el signo del error.<br />
<br />
Ejemplo: Para el μA741, IB = 80nA e IOS = 20nA. Determine el error en el<br />
voltaje de salida si R1 = 22kΩ, R2 = 2.2MΩ, y<br />
(a) despreciamos IOS y Rx = 0;<br />
<br />
Respuesta:<br />
<br />
EO =(2.2 × 106)(80 × 10−9)= 176mV<br />
(b) Rx = 22kΩ 2.2MΩ = 21782Ω;<br />
<br />
Respuesta:<br />
<br />
EO = ±IOSR2 = ±20nA × 2.2MΩ = ±44mV<br />
<br />
<strong>Nivel (Offset) en el voltaje de entrada, VOS</strong><br />
<br />
Debido a imperfecciones en le construcci´on del AO, aun si conectamos ambas entradas a tierra vO = vog diferente 0V . Este error se representa como un voltaje de offset en la entrada,<br />
<br />
VOS =vog/a<br />
<br />
donde vog representa el voltaje que se mide en la salida cuando las entradas estan conectadas a tierra, y a es la ganancia de lazo abierto. El VOS usualmente se representa como una fuente d.c. conectada a la entrada + del AO, y es amplificado igual que cualquier señal conectada a dicho punto.<br />
<br />
El valor de VOS no es constante, y cambia linealmente con temperatura. Coeficientes<br />
tıpicos son: 5mV/◦C (741) y 0.1mV/◦C (OP-77).<br />
<br />
Ademas, la presencia de un voltaje comun a las dos entradas (llamado voltaje de modo<br />
comun, o vCM) produce un cambio dado por<br />
<br />
dVOS/dvCM =1/CMRR<br />
<br />
donde el common-mode rejection ratio (CMRR) es un parametro que se reduce a medida<br />
que la frecuencia de la señal comun aumenta, haciendo que VOS aumente con la frecuencia de vCM.<br />
<br />
Tambien variaciones en el voltaje de la fuente de potencia afectan el valor de VOS, de acuerdo a la formula<br />
<br />
dVOS/dVS=1/PSRR<br />
<br />
donde PSRR representa un parametro llamado el power-supply rejection ratio.<br />
Por ultimo, la señal de salida vO producen cambios en la entrada diferencial del AO que afectan VOS, ΔVOS = ΔvO/ a .<br />
<br />
Todas estas variaciones pueden combinarse en la siguiente expresion<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhoZ8EdZ4DturwcvjJh35-3WvPYLB0m9Mci3v0zzVB2yKC44bo2EryybIgkYrud_nyu8oh2x9d271_WC6_l3OFKmh5KRClAyVXplgjWqd2WIxZUpt_f42rrAJHE1R585n-jCuh2kYDZc19/s1600/14.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487562508425452674" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhoZ8EdZ4DturwcvjJh35-3WvPYLB0m9Mci3v0zzVB2yKC44bo2EryybIgkYrud_nyu8oh2x9d271_WC6_l3OFKmh5KRClAyVXplgjWqd2WIxZUpt_f42rrAJHE1R585n-jCuh2kYDZc19/s320/14.JPG" style="cursor: hand; height: 243px; width: 320px;" /></a><br />
<br />
<strong>Cancelacion del error debido a VOS y a IOS</strong><br />
<br />
Si el error producido por VOS e IOS excede los limites impuestos por la aplicaci´on, es necesario corregirlo añadiendo un voltaje externo que cancela el error. Esto implica que cada circuito tiene que ser ajustado en el campo, pues solo se conocen los valores limites del error y no su valor o polaridad. Algunos AO tienen terminales especiales que permiten la correccion del error d.c producido por VOS e IOS, y en este caso las publicaciones asociadas deben presentar su uso correcto. Los siguientes diagramas muestran alternativas que pueden usarse cuando<br />
dichos terminales no estan disponibles:<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEji3vN8gLDNCs0OYoMptCazLkXBbxbhz0kPSYcED3vY0ab1pqHEBbYJC8uCrXWCeuSFdKO9PLCUdUvOguasRDwEIAjFIGezr6OiY4-CZW3E7VdQPW0SUtjYzuUTcs03L1CWVp4uFs9XlXPH/s1600/15.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487563066353722466" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEji3vN8gLDNCs0OYoMptCazLkXBbxbhz0kPSYcED3vY0ab1pqHEBbYJC8uCrXWCeuSFdKO9PLCUdUvOguasRDwEIAjFIGezr6OiY4-CZW3E7VdQPW0SUtjYzuUTcs03L1CWVp4uFs9XlXPH/s320/15.JPG" style="cursor: hand; height: 224px; width: 320px;" /></a><br />
<br />
Circuitos para anular el error dc<br />
Nombre Alexander Sayago<br />
C.I:16.232.455<br />
Seccion 1 Materia Estado solidoTecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-44007275960844242382010-06-26T23:30:00.002-04:302010-06-27T19:27:41.928-04:30Proyecto basicos realizados con amplificadoresLos amplificadores operacionales, también conocidos como amp-op tienen dos entradas, invertida (-) y no invertida (+), y una salida. La polaridad de la señal aplicada a la entrada invertida se invierte a la salida. Una señal aplicada a la entrada no invertida mantiene la polaridad en la salida.<br />
<br />
<br />
La ganancia (grado de amplificación) de un amplificador operacional está determinada por una resistencia de retroalimentación que alimenta parte de la señal amplificada de la salida a la entrada invertida. Esto reduce la amplitud de la señal de salida, y con ello la ganancia. Mientras mas pequeña es esta resistencia menor será la ganancia.<br />
<br />
<strong>Consideraciones generales</strong><br />
<br />
1.Los cables de alimentación de un amp-op deben ser cortos, si tienen mas de 150 mm de largo, debe colocarse un condensador de 0.1µf entre cada entrada y tierra para evitar funcionamiento errático u oscilaciones. <br />
<br />
2.Usualmente pueden sustituirse unos amp-op por otros en un circuito, por ejemplo, puede usar un amp-op doble IC-1458 en un circuito que requiera dos amp-op simples IC-741, teniendo cuidado en la conexión correcta de las patas. <br />
<br />
3.Nunca aplique una señal de entrada a un amp-op sin alimentación de voltaje.<br />
<br />
4.Siempre los voltajes de entrada V+ y V- deben ser iguales en magnitud. <br />
<br />
5.El voltaje de la señal de entrada nunca debe ser superior al voltaje de alimentación.<br />
<br />
En todos los circuitos presentados en esta página se usarán los amp-op populares IC-741 e IC-1458, el primero simple y el segundo doble.<br />
<br />
<strong>IC-741</strong><br />
<br />
El IC-741 es un amp-op de propósito general muy utilizado, es fácil de usar, práctico y barato.<br />
<br />
La figura 1 muestra un esquema de este amp-op indicando la función de sus patas.<br />
<br />
<strong>Características técnicas</strong><br />
<br />
1. Voltaje de anulación de salida-----------2 a 6 mV<br />
2. Resistencia de la pata de entrada-----0.3 a 2 megaohms<br />
3. Ganancia----------------------------------------------20,000 a 200,000 <br />
4. Corriente de consumo -----------------------1.7 a 2.8 mA<br />
5. Consumo de potencia-------------------------50 a 85 mW <br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhFkqHAFbBEqPrN4nxtGRvYkCdxsEZCin0lXXqaK3IWGEPEVp-nJ22XISQoEnkTU8CKeUxMifnFNN9Saa5O9Ws6iUPrEeDXUcjTsjsLWg3RchDqgH0OgJh3rlBNIhhtzWhhAc2F0D3HVTaO/s1600/1.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487291305094153906" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhFkqHAFbBEqPrN4nxtGRvYkCdxsEZCin0lXXqaK3IWGEPEVp-nJ22XISQoEnkTU8CKeUxMifnFNN9Saa5O9Ws6iUPrEeDXUcjTsjsLWg3RchDqgH0OgJh3rlBNIhhtzWhhAc2F0D3HVTaO/s320/1.JPG" style="cursor: hand; height: 374px; width: 449px;" /></a><br />
<br />
<br />
<br />
<strong>Valores máximos utilizables</strong><br />
<br />
1. Voltaje de suministro ±18 v <br />
2. Disipación de potencia 500 mv <br />
3. Voltaje diferencial de entrada ±30 v <br />
4. Voltaje de entrada ±15 v <br />
5. Tiempo en corto-circuito indefinido <br />
6. Temperatura de operación 0° C a 70° C <br />
<br />
<strong>IC-1458</strong><br />
El IC-1458 incluye dos amp-op independientes de propósito general en un solo paquete. Estos dos amp-op comparten las patas de voltaje de alimentación. Puede utilizarse para sustituir dos IC-741.<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjQJo6dZZz0HDTU0wuR450Hrvee_SqnqnqaZCWhXpvK3o2gsZpFEj9O4hMCUksV4OnvYkBEaBI5W-5QXZgsYAVlPi4-vYkvK5edf2u9_sBHcPgWAT5zZYeRa9ioj0dqsrTm4NQcU8NU7KDH/s1600/2.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487291736734263026" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjQJo6dZZz0HDTU0wuR450Hrvee_SqnqnqaZCWhXpvK3o2gsZpFEj9O4hMCUksV4OnvYkBEaBI5W-5QXZgsYAVlPi4-vYkvK5edf2u9_sBHcPgWAT5zZYeRa9ioj0dqsrTm4NQcU8NU7KDH/s320/2.JPG" style="cursor: hand; height: 371px; width: 499px;" /></a><br />
<br />
La figura 2 muestra un esquema de este amp-op indicando la función de sus patas. <br />
<br />
<strong>Proyectos</strong><br />
<br />
<strong>Proyecto 1: Mezclador de audio</strong><br />
En la figura 3 se muestra el diagrama de como usar un IC-741 como mezclador de diferentes entradas de audio.<br />
En este caso la salida será la mezcla de todas las entradas.<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjb44WAw89J59aRxa2ZaJURF755LAu9UQD1jadqOnUTigJxbw9k2L1BLbTUgV60xpQeJhJ3mNsNM3PJ-m2iMlpVgIXd4NemmH8MYQ2fipBPXPF95liBtkN9hboeZmPuui05vXebzpfeH9Cg/s1600/3.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487292063873932210" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjb44WAw89J59aRxa2ZaJURF755LAu9UQD1jadqOnUTigJxbw9k2L1BLbTUgV60xpQeJhJ3mNsNM3PJ-m2iMlpVgIXd4NemmH8MYQ2fipBPXPF95liBtkN9hboeZmPuui05vXebzpfeH9Cg/s320/3.JPG" style="cursor: hand; height: 366px; width: 516px;" /></a><br />
<br />
<strong>Proyecto 2: Sumador de voltajes</strong><br />
<br />
En la figura 3 se muestra como usar un amplificador operacional para sumar voltajes de entrada. La señal de salida es de polaridad invertida a las entradas.<br />
La suma de los voltajes de entrada debe ser siempre menor que el voltaje de alimentación en 1 ó 2 voltios.<br />
<br />
Pueden ser múltiples entradas pero siempre hay que usar una resistencia de 10k en cada una.<br />
<br />
En la figura 5 se muestra como lograr el mismo efecto manteniendo la polaridad de la señal de entrada a la salida. Pueden utilizarse dos IC-741 en lugar del IC-1458 siempre que se conecten adecuadamente las patas. <br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgXywpFhYypMo3LrP5IMiREASoZRteR9TvWjZubt977SUpgGdcCtsHFW7i1JClX2Se7yRWI85XkACDAjOo46bbrXsSlqA93mSgEvYdWRb-12wQsoKgxznQr3lJ7CKiAYS84AZjkdgpbILcM/s1600/4.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487292413337419954" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgXywpFhYypMo3LrP5IMiREASoZRteR9TvWjZubt977SUpgGdcCtsHFW7i1JClX2Se7yRWI85XkACDAjOo46bbrXsSlqA93mSgEvYdWRb-12wQsoKgxznQr3lJ7CKiAYS84AZjkdgpbILcM/s320/4.JPG" style="cursor: hand; height: 342px; width: 512px;" /></a><br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiSBejknxf9iBwyfjY4ibW5qN_8VnGBnpmQ9TnpL9fVhnTmgfl_7flG-XOFHu7vgLNAgGMr_qZpKHB_JWkEwiHfYnORbrEL1y05MZQpdTkwLCYLVvRo4xYzcLW14ajC1vRUQZ3Ok4lDpYtv/s1600/5.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487292655752659538" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiSBejknxf9iBwyfjY4ibW5qN_8VnGBnpmQ9TnpL9fVhnTmgfl_7flG-XOFHu7vgLNAgGMr_qZpKHB_JWkEwiHfYnORbrEL1y05MZQpdTkwLCYLVvRo4xYzcLW14ajC1vRUQZ3Ok4lDpYtv/s320/5.JPG" style="cursor: hand; height: 306px; width: 527px;" /></a><br />
<br />
<br />
<br />
<strong>Proyecto 3: Diferenciador de voltajes</strong><br />
<br />
En la figura 6 se muestra un diagrama de como hacer la resta de dos voltajes, en este caso la salida será igual a Vent2 ¯ Vent1. El voltaje de la señal no puede superar al voltaje de alimentación.<br />
<br />
La polaridad del voltaje de salida será igual al de las entradas.<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjTf8zzDo-U9jAl-ufYekMhti_abW7KpXrFIUPk7YytiGgAz783CAFSpjZn_pO1Ws4sAGY9skxxOA5DVKxcBGHLo2TWO3_LKvwVf2hQyxA4dCCQhQklHknIXp8Lh-D0GfIiDkbnqeDcvZkf/s1600/6.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487292911275600226" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjTf8zzDo-U9jAl-ufYekMhti_abW7KpXrFIUPk7YytiGgAz783CAFSpjZn_pO1Ws4sAGY9skxxOA5DVKxcBGHLo2TWO3_LKvwVf2hQyxA4dCCQhQklHknIXp8Lh-D0GfIiDkbnqeDcvZkf/s320/6.JPG" style="cursor: hand; height: 331px; width: 546px;" /></a><br />
<br />
<br />
<strong>Proyecto 4: Interruptor permutador (flip-flop)</strong><br />
El circuito de la figura 7 usa un chip analógico para ejecutar una función digital lógica. En dependencia de a donde se conecte la entrada E se encenderá uno u otro LED.<br />
<br />
Los diodos D1 y D2 son diodos zener opcionales y sirven para limitar el nivel de la salida al valor del umbral de conexión de los zener, diodos de 5.1 voltios son razonables.<br />
<br />
Este circuito tiene "memoria" es decir el estado adquirido se mantiene aunque la entrada flote después de disparado en una dirección.<br />
Funciona de la manera siguiente:<br />
Entrada E LED 1 LED 2<br />
+V on off<br />
-V off on<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgLPPTHYjq42EpIl2vb5OKRB2_SemEPoVXcZ4mDitlvOT_mxd7SRCAEIU_SpBZe_AjUp3CGo2FyTgpEeAHcqeVRkG7GG61J1HkcR21kIftSzxLbpWSb0YI0wEoM-lhMW3a3PKiTdKFakaAn/s1600/7.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487293247866408178" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgLPPTHYjq42EpIl2vb5OKRB2_SemEPoVXcZ4mDitlvOT_mxd7SRCAEIU_SpBZe_AjUp3CGo2FyTgpEeAHcqeVRkG7GG61J1HkcR21kIftSzxLbpWSb0YI0wEoM-lhMW3a3PKiTdKFakaAn/s320/7.JPG" style="cursor: hand; height: 406px; width: 659px;" /></a><br />
<br />
<br />
<br />
<strong>Proyecto 5: Filtro de paso de bajas frecuencias</strong><br />
<br />
La figura 8 representa un circuito que sirve para reducir la potencia de las altas frecuencias a la salida por encima del valor de frecuencia fcen la señal de entrada, en él:<br />
<br />
R1 = R2 = R<br />
C1 = C2 = C<br />
<br />
R3 = 0.586 ×R4<br />
Ganancia = R4/R3<br />
Se considera la frecuencia de corte fc, a la frecuencia donde la señal de salida es 0.707 el valor de la señal máxima de salida.<br />
La magnitud de la reducción de las altas frecuencias será mayor a medida que esta sube.<br />
Si se usan:<br />
R= 4700 ohmios <br />
C= 0.01 µf<br />
fc= 3,386 Hz<br />
Estos valores no son exactos, debe probar con diferentes componentes para lograr un propósito determinado<br />
<br />
<strong>Proyecto 6: Filtro de paso de altas frecuencias</strong><br />
<br />
Este circuito es identico al anterior de pasa-bajos excepto que R1, R2 y C1, C2 han sido intercambiados. Esto produce el efecto contrario, reduce el paso de las altas frecuencias.<br />
Las consideraciones y el valor de fcson las mismas del caso anterior.<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi2ZY0HlscfP5iJzZEm5qsB1jClRYXp_NE5nS-j1rwPgFz78vu8plwzbdAU8u6ZGMd3lHvdwEN5h1qaQCfKdBFhLhi3CsaJ1F0ySkxGZgAKvoLVxbMk4S6crW7JLkbiPB7ZDid7SnJyxq5S/s1600/9.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487293545344970402" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi2ZY0HlscfP5iJzZEm5qsB1jClRYXp_NE5nS-j1rwPgFz78vu8plwzbdAU8u6ZGMd3lHvdwEN5h1qaQCfKdBFhLhi3CsaJ1F0ySkxGZgAKvoLVxbMk4S6crW7JLkbiPB7ZDid7SnJyxq5S/s320/9.JPG" style="cursor: hand; height: 293px; width: 501px;" /></a><br />
<br />
<strong>Proyecto 7: Filtro pasa-banda sintonizable</strong><br />
<br />
En la figura 10 se muestra el circuito para construir un filtro pasa-banda de frecuencias. Este filtro puede ser sintonizado usando el potenciómetro, para dejar pasar desde un estrecho rango de algunos cientos de Hz hasta alrededor de 3000 Hz.<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiZ8j_dvgfKvHUOrR5y1TLm0HWnLkdqHawALQ7M8upzlz5F3js-a6lvkifAPnH6p_2VrCz0IXNFKSz-CNvKLvU_9NbE7RKZPiAFaLb6HE-rUZ3bcCHS159Ff-mXMzJLVwp9vQ3gNn8JvuC9/s1600/10.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487293968532854306" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiZ8j_dvgfKvHUOrR5y1TLm0HWnLkdqHawALQ7M8upzlz5F3js-a6lvkifAPnH6p_2VrCz0IXNFKSz-CNvKLvU_9NbE7RKZPiAFaLb6HE-rUZ3bcCHS159Ff-mXMzJLVwp9vQ3gNn8JvuC9/s320/10.JPG" style="cursor: hand; height: 306px; width: 534px;" /></a><br />
<br />
<br />
<strong>Proyecto 8: Generador de ondas cuadradas</strong><br />
<br />
Este circuito es facilmente ajustable para generar ondas cuadradas. Los componentes de tiempo son C1, R4, R5, R6, y R7.<br />
Los componentes R1, R2 y R3 controlan la duración de los pulsos (ancho). Los pulsos son simétricos cuando R2 está en su centro.<br />
Puede conectarse R2 directamente a +V y tierra eliminando a R1 y R3.<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiA5K7mPQ__znpj8O3bWeBB5k6FofWbbxfFuhSvejhHLNJI_yU_AAup1MHzGleKuyMZkX4mWgm80NfKbmsTbPVGqof_SqMAGX7AZSAPYjMeR1wJBQZ7Li32sUtm2FhzEOhM98vEOf88OItg/s1600/11.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487294192246974930" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiA5K7mPQ__znpj8O3bWeBB5k6FofWbbxfFuhSvejhHLNJI_yU_AAup1MHzGleKuyMZkX4mWgm80NfKbmsTbPVGqof_SqMAGX7AZSAPYjMeR1wJBQZ7Li32sUtm2FhzEOhM98vEOf88OItg/s320/11.JPG" style="cursor: hand; height: 350px; width: 536px;" /></a><br />
<br />
Nombre :Alexander Sayago<br />
C.I:16.232.455<br />
Seccion 1 Materia: Estado SolidoTecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-53647263090537986252010-06-26T23:26:00.002-04:302010-06-27T19:27:15.006-04:30Aplicaciones con amplificadores operacionalesVamos a ver algunas aplicaciones básicas más que podemos encontrar hachas con los amplificador operacionales. Existen muchas más y prácticamente el límite lo establece el ingenio y habilidad del diseñador electrónico.<br />
<br />
<br />
<strong>1) AMPLIFICADORES LINEALES</strong><br />
<br />
Para poder utiliza un amplificador operacional como un amplificador lineal es decir, la salida es una copia de la entrada pero amplificada, deberemos hacer una realimentación de la salida en la entrada invertida del op-amp. Dependiendo de cómo se haga esa realimentación de la señal de salida, se crearán distintos amplificador lineales con diferentes características.<br />
<br />
Para esta explicación, emplearemos un divisor de tensión o voltaje, a fin de tomar solo una muestra de la señal de salida que llevaremos a la entrada invertida.<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEilvmMYR9U6LndftT-S_gy9ujkQm3o5yYFUQps762tSD3-_UZTHQwdDDKp4uwjdDj7BKW_OA1z79-K37J5P4cfpCWooO-R4YAoIIj1AK6KASd86StIUSdty-ckP6Vh3CIoWgCdSsWANkuCf/s1600/1.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487288330518917858" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEilvmMYR9U6LndftT-S_gy9ujkQm3o5yYFUQps762tSD3-_UZTHQwdDDKp4uwjdDj7BKW_OA1z79-K37J5P4cfpCWooO-R4YAoIIj1AK6KASd86StIUSdty-ckP6Vh3CIoWgCdSsWANkuCf/s320/1.JPG" style="cursor: hand; height: 354px; width: 448px;" /></a><br />
<br />
<br />
<br />
<br />
Con esta configuración hacemos un AMPLIFICADOR LINEAL NO INVERSOR.<br />
<br />
Al hacer la realimentación, se establece lo que se denomina "Ganancia de lazo". Esta ganancia, que hemos marcado como G', viene dada por la siguiente ecuación:<br />
<br />
G' = (R1/R2) + 1<br />
<br />
y se de debe diseñar para que sea mucho menor que G, la ganancia del amplificador<br />
<br />
En estas condiciones, la resistencia de entrada de todo el amplificador se ve modificada y valdrá:<br />
<br />
Ri' = Ri * (G/G')<br />
<br />
y la de salida será:<br />
<br />
Ro' = Ro * (G`/G)<br />
Fíjense como la resistencia de entrada se incrementa mucho con el lazo de realimentación mientras que la de salida se disminuye significativamente. En la práctica se alcanzan valores de Ri mayores a 1M Ohm y de salida Ro menores a 1 Ohm (muy pequeña).<br />
<br />
Resumiendo las características de este amplificador tenemos que:<br />
<br />
1) La señal de salida está en fase con la de la entrada.<br />
<br />
2) La ganancia de lazo depende únicamente de R1 y R2<br />
<br />
3) La resistencia de entrada es muy grande<br />
<br />
4) La resistencia de salida es muy baja<br />
<br />
5) Su utilización típica es en amplificador de audio y circuitos de medición.<br />
<br />
6) Sirve como "aislador" de señales espurias conectadas a él, eliminándolas por la realimentación.<br />
<br />
7) La realimentación elimina los efectos negativos que pudieran aparecer entre la entrada y la salida del amplificador. <br />
<br />
Como ejemplo del punto 7, si una resistencia se conecta en serie con la salida del amplificador lineal no inversor, ella aumentará la resistencia de salida de éste en forma aditiva. Si esto no es deseado, la resistencia en serie se puede colocar dentro del lazo de realimentación reduciendo su efecto aditivo a la salida:<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiFFYrNR8jq3-Lzd5mqFhVtdn7O9KzfX0ozrSlLkvEuffUH3muytnEaoATlEq-LuIP3SzGhmyGro-TZJb3VpM9kE5soh1GMxdyK0SnpELp_YWmbiVNA6Mn5dxCAo0DkP3XSGfSEZMWp0bUG/s1600/2.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487288633980027154" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiFFYrNR8jq3-Lzd5mqFhVtdn7O9KzfX0ozrSlLkvEuffUH3muytnEaoATlEq-LuIP3SzGhmyGro-TZJb3VpM9kE5soh1GMxdyK0SnpELp_YWmbiVNA6Mn5dxCAo0DkP3XSGfSEZMWp0bUG/s320/2.JPG" style="cursor: hand; height: 305px; width: 385px;" /></a><br />
<br />
<br />
¿Se acuerdan de lo que hablamos sobre los pushpull al comienzo del minitutorial?. Ese tipo de circuitos también se utilizan para aumentar el suministro de corriente en los circuitos.<br />
<br />
Si quisiéramos aumentar la corriente a la salida de nuestro amplificador, podríamos hacer algo como esto:<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjAYwl5ISXvQWHfJvdxiWk93198AuXMLyh0zi3e72-cngrEXH_qHoSa-UhzseqKa0sGI2hfN2HcL9Dz2KtrYDosdf8BWjctk4Oz-ORVqbXLHL-KRONM4HaEO4JZ5BXy1LeWYa0t3Of8Xtl-/s1600/3.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487288900809222322" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjAYwl5ISXvQWHfJvdxiWk93198AuXMLyh0zi3e72-cngrEXH_qHoSa-UhzseqKa0sGI2hfN2HcL9Dz2KtrYDosdf8BWjctk4Oz-ORVqbXLHL-KRONM4HaEO4JZ5BXy1LeWYa0t3Of8Xtl-/s320/3.JPG" style="cursor: hand; height: 334px; width: 451px;" /></a><br />
<br />
<br />
El problema es que este tipo de circuito produce distorsión a la señal de salida.<br />
Una vez más, introduciendo el push-pull dentro del bucle de realimentación, reducimos y prácticamente eliminamos esa distorsión:<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi_7owtyuOqcZ5EvZ5bLFxyB4OiKIwKp9GgwKMw0dW5J61G2Mc9SHrMD_0XFp9ZLld-zjugrTpm7JqX-ZUFb92DBzKQZL94ssvnz_WWozFt-mRMIqyk5QMUS4MPW3kbzx0b1fiXMfhi8EY3/s1600/4.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487289352875718882" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi_7owtyuOqcZ5EvZ5bLFxyB4OiKIwKp9GgwKMw0dW5J61G2Mc9SHrMD_0XFp9ZLld-zjugrTpm7JqX-ZUFb92DBzKQZL94ssvnz_WWozFt-mRMIqyk5QMUS4MPW3kbzx0b1fiXMfhi8EY3/s320/4.JPG" style="cursor: hand; height: 318px; width: 444px;" /></a><br />
<br />
<br />
<strong>2) SEGUIDORES DE VOLTAJE</strong><br />
<br />
¿Qué pasaría si elimináramos las resistencias del divisor de tensión en el amplificador lineal y mantuviéramos el bucle de realimentación?<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjj-HmEkHfKkmyX1_8UxokO0nDEGMF5FSdxr7Gf69l0Qib62-TZfP17x7RrFmku5qV1tREfBvjHrKNjZtGRTVVd4EZNPR66VecTPRGSMIUSME0YUPe7oBldJ6LwIaGIfOKvo1HxEw1ZyMQb/s1600/5.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487289684933400594" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjj-HmEkHfKkmyX1_8UxokO0nDEGMF5FSdxr7Gf69l0Qib62-TZfP17x7RrFmku5qV1tREfBvjHrKNjZtGRTVVd4EZNPR66VecTPRGSMIUSME0YUPe7oBldJ6LwIaGIfOKvo1HxEw1ZyMQb/s320/5.JPG" style="cursor: hand; height: 340px; width: 451px;" /></a><br />
<br />
<br />
<br />
Como R1 la hemos sustituido por un cable y R2 la eliminamos, R1=0 y R2=infinito.<br />
y si vemos las ecuaciones del amplificador lineal veríamos que:<br />
<br />
G' = 1<br />
<br />
Ri' = G * Ri<br />
<br />
Ro' = Ro / G<br />
<br />
La ganancia de lazo de este amplificador es 1, y es la mínima que puede tener un amplificador lineal. Que tenga una ganancia de lazo igual a 1 implica que la señal a la entrada es exactamente igual a la de salida. A este circuito se le llama amplificador de ganancia 1 o seguidor de voltaje.<br />
<br />
<br />
Resumiendo las características de este amplificador tenemos que:<br />
<br />
8) La señal de salida está en fase con la de la entrada.<br />
<br />
9) La ganancia de lazo es 1<br />
<br />
10) La resistencia de entrada es grandísima<br />
<br />
11) La resistencia de salida es bajísima<br />
<br />
12) Su utilización típica es en acopladores de impedancia, amplificador de audio y circuitos de medición.<br />
<br />
<strong>3) AMPLIFICADOR LINEAL INVERSOR</strong><br />
<br />
Este tipo de amplificador funciona de manera similar a los no inversores, pero a la salida se obtiene una señal que está desfada en 180º respecto a la de entrada.<br />
<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhzocdPC4F2W5YR8AZoe-ApdwBSRRdhfASLNt-NthhzDoCdFNfFLPHTepL1-_cBd7pUV62t2SgxwCAZ3yxWNLGD01mxMZarUxt46RSz2JnIkhgv6ktdtxyWvoaEtzdWwR8nEUcdmn89aP9o/s1600/6.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487289997856215650" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhzocdPC4F2W5YR8AZoe-ApdwBSRRdhfASLNt-NthhzDoCdFNfFLPHTepL1-_cBd7pUV62t2SgxwCAZ3yxWNLGD01mxMZarUxt46RSz2JnIkhgv6ktdtxyWvoaEtzdWwR8nEUcdmn89aP9o/s320/6.JPG" style="cursor: hand; height: 334px; width: 422px;" /></a><br />
<br />
<br />
La ganancia de lazo y resistencias de entrada y salida de estos amplificador inversores vienen dados por las siguientes ecuaciones.<br />
<br />
G' = R1 / R2<br />
<br />
Ri' = R2<br />
<br />
Ro' = Ro * (1+G')/G<br />
<br />
<strong>4) AMPLIFICADOR SUMADOR</strong><br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhNckwfKtec8vkl7pS03j69OVsrmErztorjVgKKq25AdaffuJu83MFMwYcpoXaWyUobof8RbcB0DLYspEDFEpnzecHLQk7ZKhWbvfE_5goaq49wv8easCL0oTEW6FPBk8lmPTG2dH0Nvu0b/s1600/7.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487290313031904738" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhNckwfKtec8vkl7pS03j69OVsrmErztorjVgKKq25AdaffuJu83MFMwYcpoXaWyUobof8RbcB0DLYspEDFEpnzecHLQk7ZKhWbvfE_5goaq49wv8easCL0oTEW6FPBk8lmPTG2dH0Nvu0b/s320/7.JPG" style="cursor: hand; height: 314px; width: 453px;" /></a><br />
<br />
Este amplificador suma las señales de entrada desde R1 hasta Rn y luego son amplificadas. Si V1, V2, V3…. Vn son las señales de entrada, entonces la señal de salida Vo viene dada por:<br />
<br />
Vo = 1/Rf * (V1*R1 + V2*R2 + V3*R3 + …..Vn*Rn)<br />
<br />
Estas son algunas de las aplicaciones básicas que se pueden realizar con un amplificador operacional. Así como éstas, podemos hacer otros circuitos básicos como Rectificadores, Cambiadores de Fase, Rectificadores de Señales, Osciladores Astables, Schmitt Triggers y muchas otras más.<br />
<br />
Un aspecto importante de los amplificador operacionales que no se trata en este minitutorial, es su respuesta en frecuencia. El ancho de banda operativo de los op-amp no es infinito y depende de su diseño de fábrica, por lo que para desarrollar las aplicaciones deberemos echar mano de las "datasheet" del fabricante para observar estos parámetros. Es necesario entonces que investiguen referente a esto pues es parte fundamental de los diseño que incluyen estos componentes.<br />
<br />
Al igual que para el offset existen pines disponibles para realizar su ajuste, algunos componentes también suministran pines adicionales para realizar una compensación de respuesta en frecuencia de forma externa, por medio de circuitos RC conectados a ellos a fin de aumentar su ancho de banda.<br />
<br />
Hay mucho más que investigar respecto a los amplificador operacionales, pero conociendo los fundamentos y sus configuraciones básicas, podremos más o menos intuir la función que están realizando estos dispositivos al observar esquemáticos complejos que los incluyen.<br />
<br />
<br />
Espero que este minitutorial de amplificador operacionales, les sirva de guia básica y los motive a seguir investigando sobre éstos y otras cosas apasionantes de la electrónica.<br />
<br />
Nombre :Alexander Sayago<br />
C.I:16.232.455<br />
Seccion 1 Materia: Estado SolidoTecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-77301203205230894022010-06-26T23:23:00.002-04:302010-06-27T19:26:43.151-04:30Caracteristicas basicas del amplificador operacional<strong>AJUSTE DEL OFFSET<br />
<br />
</strong>En la primera parte de este minitutorial terminamos explicando el offset de tensión de los amplificador operacionales.<br />
<br />
Este es un efecto intrínseco no deseado de estos dispositivos que nos gustaría poder eliminar. <br />
<br />
El offset de tensión, lo podemos ajustar variando una de las entradas del amplificador a fin de que anule o compense la tensión a la salida:<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgCl_k1w7pGnWv3pjh5VDqBHRimy4LDFutSA2tEFSrRIw-vyvcAxol5IYZOIIyY8v1ZI3uWmYJf1sP-p916pnOf4oncp8MnXcetAkrfTL4BtSzu7_rxxEyj7_eWM46ilBkTV70jyGQuyejY/s1600/1.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487286130326751906" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgCl_k1w7pGnWv3pjh5VDqBHRimy4LDFutSA2tEFSrRIw-vyvcAxol5IYZOIIyY8v1ZI3uWmYJf1sP-p916pnOf4oncp8MnXcetAkrfTL4BtSzu7_rxxEyj7_eWM46ilBkTV70jyGQuyejY/s320/1.JPG" style="cursor: hand; height: 281px; width: 408px;" /></a><br />
<br />
<br />
a este procedimiento se le llama ajuste de offset o "null-balance" que es un término que solemos encontrarnos cuando leemos sobre electrónica. Este ajuste es muy importante cuando usamos los operacionales en circuitos de medición.<br />
<br />
Pero ustedes se preguntarán, "si utilizo la entrada invertida para ajustar el offset, ¿Cómo uso el amplificador?". Con esto en vista, los diseñadores proveen de dos pines en los encapsulados, que sirven para conectar la resistencia variable y ajustar el offset. <br />
<br />
A estos terminales se les acostumbran denominar como "offsettnull" en los chips de op-amp. Las hojas de datos de los operacionales indican como usar el "offset null".<br />
<br />
<strong>CORRIENTE DE BIAS</strong><br />
<br />
Ahora bien, si observaron antes el esquema básico del operacional, se habrán dado cuenta que las dos entradas son prácticamente las bases de sendos transistores.<br />
Pues como todo transistor requiere de una corriente de base y de una resistencia de base para polarizarlo.<br />
<br />
Estas corrientes de base son muy pequeñas (en el orden de nano o micro amperios en amplificador con entradas bipolares - transistores BJT) pero producirán una caída de tensión en cualquier resistencia de base que coloquemos a las entradas + o -;<br />
<br />
Para el siguiente circuito, si las dos resistencias de base en las entradas son exactamente iguales, la tensión de salida Vo del operacional debe ser cero:<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhhtUdncCLuYWfMzqLXu4dA003o8QNYLwJd4_nyK1pMDTCHAIw1zRAyXyFA-Tn_sT2SAT3nwvq3_vFSFFhP1NhPJnnpyfOG70wxL3m06jZnjFNNDhhJPiRr8So6Z4TJzVBqe_11-AwNZISr/s1600/2.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487286514718890498" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhhtUdncCLuYWfMzqLXu4dA003o8QNYLwJd4_nyK1pMDTCHAIw1zRAyXyFA-Tn_sT2SAT3nwvq3_vFSFFhP1NhPJnnpyfOG70wxL3m06jZnjFNNDhhJPiRr8So6Z4TJzVBqe_11-AwNZISr/s320/2.JPG" style="cursor: hand; height: 272px; width: 398px;" /></a><br />
<br />
<br />
Si estas resistencias difieren en su valor, el operacional tendrá una tensión de salida espuria similar a la que vimos en el offset de tensión.<br />
<br />
Por esta razón, deberemos tener mucho cuidado de que las resistencias equivalentes de los circuitos generadores de las señales en los terminales de entradas sean lo más parecidas posible entre ellas, pues si no desbalancearemos el operacional. <br />
<br />
Este offset también puede ser corregido con el "offset null". <br />
<br />
A las corrientes que circulan por Rb1 y Rb2 se les llaman corrientes de BIAS o "BIAS currents" y al desbalance que ocasiona se le llama "offset de corriente de entrada" o "Input offset Current" (Los términos en Inglés son para que se acostumbren a estos conceptos comunes en electrónica)<br />
<br />
<br />
<strong>EL AMPLIFICADOR OPERACIONAL SIN REALIMENTACIÓN</strong><br />
<br />
Veamos ahora este amplificador operacional:<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjypgt43Za_tdR5jC7qBLEXJs4G8fE2hZEtQMgHONGcQYumoJQl2WwCW5R5Hm7HNnzYObRQPeXxrb6RXbnqSBxOxQSxit_ojb_FWf7m3oBDMVAFpcaW4-y_jQZzaIjJPzQqrvXbjli3IdTf/s1600/3.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487286903012313858" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjypgt43Za_tdR5jC7qBLEXJs4G8fE2hZEtQMgHONGcQYumoJQl2WwCW5R5Hm7HNnzYObRQPeXxrb6RXbnqSBxOxQSxit_ojb_FWf7m3oBDMVAFpcaW4-y_jQZzaIjJPzQqrvXbjli3IdTf/s320/3.JPG" style="cursor: hand; height: 282px; width: 389px;" /></a><br />
<br />
Si hacemos una tabla variando Vi desde –Infinito hasta Infinito y midiendo Vo, y los graficáramos, obtendríamos una curva como la siguiente:<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj6Wcxj26vr2jVjZe9TmiymFELpYJG_U2bhyphenhyphen5FuOtF3UL182CIk9mFCzvv-BwEf0FzADAGofDwnCGASXU2XyL52IgMqxtuBXrlA3e4I0Cn1C-OPUqu3PXRX6hlG9KlkZSmC18meqpIvXz4u/s1600/4.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487287161501147442" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj6Wcxj26vr2jVjZe9TmiymFELpYJG_U2bhyphenhyphen5FuOtF3UL182CIk9mFCzvv-BwEf0FzADAGofDwnCGASXU2XyL52IgMqxtuBXrlA3e4I0Cn1C-OPUqu3PXRX6hlG9KlkZSmC18meqpIvXz4u/s320/4.JPG" style="cursor: hand; height: 282px; width: 434px;" /></a><br />
<br />
Nota: Los valores mostrados no son reales y se expresan con números sencillo con fines de facilitar el ejemplo. <br />
<br />
Este gráfico nos expresa la función de transferencia del amplificador operacional ideal. <br />
<br />
Los puntos donde la curva se hace paralela al eje Vi indican la tensión de saturación (positiva y negativa). La pendiente de la recta en la zona lineal es la ganancia G del op-amp.<br />
<br />
Escojamos dos puntos cualesquiera de la parte recta, por ejemplo: (-0,005,-10) y (0,004,8) (créanme que estos son dos puntos de la parte recta y recuerden que el eje X está en miliVoltios y el Y en Voltios, de allí los decimales); para este caso hipotético la ganancia sería:<br />
<br />
G= (8-(-10)) / (0,004-(-0,005)) = 18/0,009 = 2000 <br />
<br />
Este amplificador tendría una ganancia de G=2000.<br />
<br />
Si el amplificador operacional no tiene realimentación, el offset en sus entradas cambiará en forma descontrolada en la medida que dichas entradas varíen, haciendo que el op-amp trabaje en una forma inestable y no podremos tener lo que se llama un "punto de trabajo". Nuestro circuito estará siempre en +Vsat o en -Vsat.<br />
<br />
Para lo único que podemos usar un amplificador operacional en lazo abierto es para COMPARAR cuando una de las entradas es mayor que la otra.<br />
<br />
Así obtenemos un COMPARADOR:<br />
<br />
1. Cuando V+ es mayor que V-, la salida Vo es +Vsat<br />
2. Cuando V- es mayor que V+, la salida Vo es –Vsat<br />
<br />
No se vayan a confundir con los signos: V+ podría valer 3 milivoltios y V- unos 2 milivoltios, con lo que Vo se iría a +Vsat (+12 voltios en nuestro ejemplo). Por otro lado y en otra circunstancia V+ podría valer 3 milivoltios y V- unos 5 milivoltios, con lo que Vo se iría a -Vsat (-12 voltios en nuestro ejemplo)<br />
<br />
Recuerden que Vi = (V+) – (V-) por lo que en el primer caso Vi = 3-2 = 1 milivoltio y en el segundo caso Vi = 3 – 5 = -2 milivoltios.<br />
<br />
La curva de este COMPARADOR ideal sería algo como esto:<br />
<br />
<a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh3kjP_nDl2kLmcm_8b0v6VQG1LO3ViBMcWeSPVy2vstPoJcIwMoPUjOFadoZwD-aDFDnGR0uR6biQa14cwgBFqFs7qaO8-01O2pgnhgYKi1vH9Z8FbWL8dHfvbh3DbQDAMpH2fY6zec2-Z/s1600/5.JPG"><img alt="" border="0" id="BLOGGER_PHOTO_ID_5487287477281760530" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh3kjP_nDl2kLmcm_8b0v6VQG1LO3ViBMcWeSPVy2vstPoJcIwMoPUjOFadoZwD-aDFDnGR0uR6biQa14cwgBFqFs7qaO8-01O2pgnhgYKi1vH9Z8FbWL8dHfvbh3DbQDAMpH2fY6zec2-Z/s320/5.JPG" style="cursor: hand; height: 261px; width: 427px;" /></a><br />
<br />
<br />
Fíjense que si vemos el valor de G, esta sería INFINITO (pendiente vertical), en la realidad esto se indicado por una ganancia muy grande.<br />
<br />
Los comparadores pueden ser INVERSORES o NO INVERSORES dependiendo como conectemos las señales a la entrada del amplificador operacional.<br />
<br />
En la práctica, si queremos un comparador no inversor, pondremos la señal de referencia en la entrada invertida (V-) y la señal que queremos comparar entraría por V+. Así podemos saber cuando la señal monitoreada es mayor o menor que la referencia y actuar en consecuencia. Así, en Vo mediríamos +Vsat cuando la señal monitoreada es más grande que la de referencia y -Vsat en caso contrario. <br />
<br />
Si deseamos invertir la salida (lógica negativa), las conectaremos al revés. En este caso en Vo mediríamos -Vsat cuando la señal monitoreada es más grande que la de referencia y +Vsat en caso contrario.<br />
<br />
Nombre :Alexander Sayago<br />
C.I:16.232.455<br />
Seccion 1 Materia: Estado SolidoTecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-28941955352076869142010-06-26T19:36:00.002-04:302010-06-27T19:26:10.140-04:30Current-feedback operational amplifier<div class="post-footer-line post-footer-line-2"><span class="post-labels"> </span> </div><div class="post-footer-line post-footer-line-3"><span class="post-location"> </span> </div><a href="http://www.blogger.com/post-edit.do" name="5817562850261351753"></a><br />
<div class="post-header"></div><div class="post-body entry-content"><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_filelist.xml" rel="File-List"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_themedata.thmx" rel="themeData"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_colorschememapping.xml" rel="colorSchemeMapping"></link> <style>
<!-- /* Font Definitions */ @font-face {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4; mso-font-charset:0; mso-generic-font-family:roman; mso-font-pitch:variable; mso-font-signature:-1610611985 1107304683 0 0 159 0;} @font-face {font-family:Calibri; panose-1:2 15 5 2 2 2 4 3 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:-1610611985 1073750139 0 0 159 0;} @font-face {font-family:TimesNewRoman; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-alt:"MS Mincho"; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:0 134676480 16 0 131073 0;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {mso-style-unhide:no; mso-style-qformat:yes; mso-style-parent:""; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:0cm; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoPapDefault {mso-style-type:export-only; margin-bottom:10.0pt; line-height:115%;} @page Section1 {size:612.0pt 792.0pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} -->
</style> <br />
<div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">The current feedback operational amplifier or CFB op-amp is a type of electronic amplifier whose inverting input is sensitive to current, rather than to voltage as in a conventional voltage-feedback (VFB) operational amplifier. The CFB op-amp was invented by David Nelson at Comlinear Corporation, and first sold in 1982 as a hybrid amplifier, the CLC103. The first patent covering a CFB op-amp is , David Nelson and Kenneth Saller (filed in 1983). The first integrated circuit CFB op-amps were introduced in 1987 by both Comlinear and Elantec (designer Bill Gross). They are usually produced with the same pin arrangements as VFB op-amps, allowing the two types to be interchanged without rewiring when the circuit design allows. In simple configurations, such as linear amplifiers, a CFB op-amp can be used in place of a VFB op-amp with no circuit modifications, but in other cases, such as integrators, a different circuit design is required. The classic four-resistor differential amplifier configuration also works with a CFB op-amp, but the common-mode rejection ratio is poorer than that from a VFB op-amp.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><b>Operation</b></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">Referring to the schematic shown, the section marked in red forms the input stage and error amplifier. The inverting input (node where emitters of Q1 & Q2 are connected) is low-impedance and hence sensitive to changes in current. Resistors R1–R4 set up the quiescient bias conditions and are chosen such that the collector currents of Q1 & Q2 are the same. In most designs, active biasing circuitry is used instead of passive resistive biasing, and the non-inverting input may also be modified to become low impedance like the inverting input in order to minimise offsets.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">With no signal applied, due to the current mirrors Q3/Q4 & Q5/Q6, the collector currents of Q4 and Q6 will be equal in magnitude if the collector currents of Q1 and Q2 are also equal in magnitude. Thus, no current will flow into the buffer's input (or equivalently no voltage will be present at the buffer's input). In practice, due to device mismatches the collector currents are unequal and this results in the difference flowing into the buffer's input resulting in an offset at its output. This is corrected by adjusting the input bias or adding offset nulling circuitry.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">The section marked in blue (Q3–Q6) forms an I-to-V converter. Any change in the collector currents of Q1 and Q2 (as a result of a signal at the non-inverting input) appears as an equivalent change in the voltage at the junction of the collectors of Q4 and Q6. Cs is a stability capacitor to ensure that the circuit remains stable for all operating conditions. Due to the wide open-loop bandwidth of a CFB amplifier, there is a high risk of the circuit breaking into oscillations. Cs ensures that frequencies where oscillations might start are attenuated, especially when running with a low closed-loop gain.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">The output stage (in cyan) is a buffer which provides current gain. It has a voltage gain of unity (+1 in the schematic).</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><b>VFB and CFB compared</b></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">The main reasons for choosing a CFB op-amp are to obtain a greater slew rate, and to avoid the constant gain-bandwidth product of VFB types. The bandwidth of a CFB op-amp depends only on the value of its feedback resistor. It is a common misconception that the CFB has an inherently higher bandwidth.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">When CFB op-amps were first introduced, their bandwidths were huge compared to those of VFB types, making them desirable in high-frequency applications such as video and radiofrequency amplifiers adding to their reputation as high bandwidth amplifiers. Early models also had a reputation for instability, as the slightest parasitic capacitance at their inverting inputs caused them to oscillate. As the products matured, and circuit designers gained experience, the CFB op-amp became accepted as a standard circuit component. Meanwhile, the designers of VFB op-amps were forced to improve the bandwidths of their products, with the result that very fast VFB op-amps are now available.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">CFB op-amps have very high slew rates, making them useful in video amplification where slew-rate limitation leads to distortion.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">One of the trade-offs that designers must consider when choosing CFB op-amps is that these devices have high DC offsets. This makes them less suitable for high-precision or high-gain applications such as instrumentation amplifiers, and measuring instruments in general.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">CFB op-amps also have higher current noise than VFB types, precluding their use as photodiode amplifiers. In other applications, their low voltage noise can be an advantage.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">Finally, CFB op-amps are not optimised for single-supply operation, since the traditional output stage cannot swing closer than about 1.3V to the supply or ground.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">Hernández Caballero Indiana<br />
Asignatura: CAF<br />
Fuente:<a href="http://www.reference.com/browse/wiki/Current-feedback_operational_amplifier">http://www.reference.com/browse/wiki/Current-feedback_operational_amplifier</a> </span></div></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-35345263868915029292010-06-26T19:32:00.002-04:302010-06-27T19:25:32.612-04:30Application basics when using wideband voltage and current feedback op amps, Part 2 (of 2)<div class="post-header"></div><div style="text-align: justify;"><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Understand the basics of current and voltage feedback op amps and where they fit, along with constraints and implications</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">With both current and voltage feedback operational amplifiers (op amp) available to the system designer, how do you decide which one to use? This article is the second of two parts. It reviews several applications that are most suitable to the current feedback type, then it introduces the fully differential amplifier (FDA). All applications covered in Part 1 for voltage feedback op amps are also suitable for an FDA, but some particularly useful applications for this type of amplifier are shown here.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Keep in mind that applications requiring flexibility in the gain setting network will benefit from the gain bandwidth independence of the current feedback (CFB) design. As described in Part 1, the loop gain equation for a CFB includes only the feedback impedance while the gain element can be varied freely with minimal bandwidth interaction. The following examples exploit that advantage in several situations where a CFB would be the preferred solution.</span></span><br />
<br />
<b><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Example A</span></span></b><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">If an inverting summing amplifier is required with a signal bandwidth that is independent of the number of channels summed or the required gains in those channels, a CFB amplifier should be used. Figure 1 shows an example of this approach using the high output voltage and current THS3091.</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEifFldESJvMKlPLdmRcgpp9QW9uv6ucZLPzzysVUFWfFJlwtDVW65PO6rb421fkfVgll2wPH4Y9-uMTmJIN2x0HyQ3yRx0LYSviNyjg46ejFJVFWKXDgBj6twGEBa8LmKk4P2yg1Z80P_A/s1600/C0154p2-Figure1.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="176" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEifFldESJvMKlPLdmRcgpp9QW9uv6ucZLPzzysVUFWfFJlwtDVW65PO6rb421fkfVgll2wPH4Y9-uMTmJIN2x0HyQ3yRx0LYSviNyjg46ejFJVFWKXDgBj6twGEBa8LmKk4P2yg1Z80P_A/s400/C0154p2-Figure1.jpg" width="400" /></a></div><div style="text-align: justify;"><span style="font-size: small;"></span></div><div style="text-align: justify;"><span style="font-size: small;"></span></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"></span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 1. Inverting summing amplifier using the high voltage/current THS3091.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Here, we assume a 0 Ω source for each of the signal sources where each channel would see a gain of "2 V/V. For these CFB designs, the feedback resistor is first picked to be close to the recommended value for that particular CFB amplifier. Then, each input resistor should be selected according to the gain required by that channel.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Recall that this circuit implemented with a voltage feedback (VFB) has a bandwidth set by the noise gain (NG). For instance, five channels summed with a gain of -2 V/V will have a noise gain of 11. This condition would set a bandwidth for all five channels reduced to the [gain bandwidth product (GBP)]/11 even though each signal only sees a gain of -2 V/V. Using a CFB for this application retains the bandwidth much better because the parallel combination of all gain resistors does not enter strongly into the loop gain equation.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">By way of comparison, Figure 2 simulates a single channel of Figure 1 using first the CFB TH3091, then a similar VFB THS4031. The THS4031 is a low-noise, high-voltage VFB that offers approximately 200 MHz GBP.</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"><br />
</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjUqQq_1VY84dVxyA0HSqOmQFRvpdWY1L_35tTm_8RbhEsgBFBBEtWv7fBT_gcyyYzRn3773XeXPnhA1Z4Dr-wqLcQqSL-xgjHNsF5FIK0U4G_6ZU_UVAknHq3_aPbVHIu28-Wp8oPqaG0/s1600/C0154p2-Figure2.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjUqQq_1VY84dVxyA0HSqOmQFRvpdWY1L_35tTm_8RbhEsgBFBBEtWv7fBT_gcyyYzRn3773XeXPnhA1Z4Dr-wqLcQqSL-xgjHNsF5FIK0U4G_6ZU_UVAknHq3_aPbVHIu28-Wp8oPqaG0/s320/C0154p2-Figure2.jpg" /></a></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"><br />
</span></span></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 2. Comparative frequency response for one channel of Figure 1 using THS3091 and THS4031.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The circuit of Figure 1 produces a noise gain of 11, which shows up as a signal bandwidth close to 18 MHz for the THS4031, while the THS3091 gives about 200 MHz for each channel.</span></span><br />
<b><br style="font-family: Verdana,sans-serif;" /><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Example B</span></span></b><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Where frequency response peaking is required, a CFB amplifier permits this characteristic to be achieved with reduced interaction between the gain shaping and the amplifier bandwidth. Figure 3 shows an example single stage of a zero/pole pair using a high output current OPA691 CFB amplifier</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjVeqAIUZ9jS5QlpC7l5YnjRtPwwIBlQfWLDKxJUnYVjMYFiDkGas5bpOTdAzhFPMucXpAYnfMThJILN5r1JDVY0_1Y7VibgIDt8EjHCo6VWoo-DeMmSXWHo5HL_O0fNJ_TKoq_nNX09UQ/s1600/C0154p2-Figure3.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjVeqAIUZ9jS5QlpC7l5YnjRtPwwIBlQfWLDKxJUnYVjMYFiDkGas5bpOTdAzhFPMucXpAYnfMThJILN5r1JDVY0_1Y7VibgIDt8EjHCo6VWoo-DeMmSXWHo5HL_O0fNJ_TKoq_nNX09UQ/s320/C0154p2-Figure3.jpg" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"></span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 3. Frequency response peaking circuit using the OPA691.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">This example transitions from a gain of 2 V/V (6 dB) to a gain of +20 V/V (26 dB) over a 2 MHz to 20 MHz span. Implementing this design with a VFB requires a minimum gain bandwidth product (GBP) in excess of (20 × 20 MHz) = 400 MHz in order to not immediately roll off at the maximum gain setting.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 4 shows this simulation where the improved performance of the CFB OPA691 is apparent.</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglcJc_JBWOOcX8qmu7c27MhAv_5l3T8XxKFctALdbBWEJDeb2ZhFTKwJg32m_3asrf-JeyAIKU6f1fjy93wPpdRl55Yt6YikgAHDUqyacFc-FMavBnKlAtJXmRCQ4xLSL4KAaZyG9OEkU/s1600/C0154p2-Figure4.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglcJc_JBWOOcX8qmu7c27MhAv_5l3T8XxKFctALdbBWEJDeb2ZhFTKwJg32m_3asrf-JeyAIKU6f1fjy93wPpdRl55Yt6YikgAHDUqyacFc-FMavBnKlAtJXmRCQ4xLSL4KAaZyG9OEkU/s320/C0154p2-Figure4.jpg" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 4. Peaking circuit frequency response with CFB (OPA691) and VFB (OPA690).</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">As a comparison, Figure 4 also shows the high output current OPA690 VFB; note that the 300 MHz GBP of the OPA690 is not quite enough for this application while the CFB OPA691 achieves the maximum 26 dB gain at 20 MHz and remains there up to an approximate -3 dB bandwidth of 100 MHz.</span></span><br />
<br />
<b><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Example C</span></span></b><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Sallen-Key, or voltage-controlled voltage source, active filters need a non-inverting gain amplifier that has a bandwidth far in excess of the desired filter bandwidth. While this type of filter can be implemented with VFB devices quite well, a CFB device would be preferred where higher frequency cutoff filters are needed, or where the amplifier gain needs to be flexible. The amplifier gain enters into the ideal filter transfer function as part of the Q setting equation. This gain also sets the low frequency gain in a low-pass filter design.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The local bandwidth of the op amp used in this design moves the actual filter poles away from the design targets. In the Sallen-Key low-pass filter, the actual poles move down and to the right in the complex s-plane. This shift gives an actual filter that has lower 0 and higher Q than targeted. To the extent that the amplifier bandwidth changes with gain setting, as it would with a VFB amplifier, the actual filter poles are impacted more strongly using a VFB over a range of gains in the design.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Using a CFB in this filter normally allows a more solid pole placement where the amplifier gain can be varied more freely in the design process because there will be minimal interaction between the required amplifier gain and the impact on the final filter pole locations.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 5 shows an example 20 MHz low-pass Butterworth filter implemented using the CFB OPA695 that gives a passband gain of +4 V/V.</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEicCYgott9YOfkfvg2d-KeOO7Wb2p0hqSKJBZrDoh8lnI8dNO94txhDmdJLG8Vu0Yur8jvbCZd8Q3kJrovQJcBLmapAlMNyAGPVSFVMnQ4LDhxiOIl7TJVIzL4_bat1DwpPVBeWKqvTaqQ/s1600/C0154p2-Figure5.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="237" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEicCYgott9YOfkfvg2d-KeOO7Wb2p0hqSKJBZrDoh8lnI8dNO94txhDmdJLG8Vu0Yur8jvbCZd8Q3kJrovQJcBLmapAlMNyAGPVSFVMnQ4LDhxiOIl7TJVIzL4_bat1DwpPVBeWKqvTaqQ/s400/C0154p2-Figure5.jpg" width="400" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 5. Second-order, low-pass, 20 MHz Butterworth filter using the CFB OPA695.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The resistor values have been adjusted slightly from an ideal analysis to account for the amplifier bandwidth effects and hit the desired frequency response exactly.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">In this design, the OPA695 gives an amplifier bandwidth >400 MHz at a gain of +4 V/V (12 dB). This bandwidth gives a 20x margin to the desired filter poles. It is this bandwidth margin that allows the filter poles to be implemented with minimal production variation and holds the stop band rejection down to higher frequencies. All Sallen-Key filters show an increasing gain (or reduced stop band rejection) at very high frequencies as the closed loop output impedance of the amplifier increases sufficiently to support a feed through path through the filter feedback capacitor.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">As a comparison, Figure 6 shows the filter of Figure 5 simulated first with the OPA695 and then with the VFB OPA820. Operating at a gain of +4 V/V, the OPA820 will have a bandwidth of about 80 MHz.</span></span></div><div style="text-align: justify;"><span style="font-size: small;"></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhkwXOsL19p68Gj_YVii4IMP_d9l7RNW2PIPdpHIdeqZMsZXmFhQ_npEDUYXECQVkMxhe6fB_Q88ZZbSEVPn6DkPznVOeyiBDQYwkK0yOT_rz4FRfZxJIfH0kgrZ783C8dMM0PkqitJcE/s1600/C0154p2-Figure6.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhkwXOsL19p68Gj_YVii4IMP_d9l7RNW2PIPdpHIdeqZMsZXmFhQ_npEDUYXECQVkMxhe6fB_Q88ZZbSEVPn6DkPznVOeyiBDQYwkK0yOT_rz4FRfZxJIfH0kgrZ783C8dMM0PkqitJcE/s320/C0154p2-Figure6.jpg" /></a></div><div style="text-align: justify;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"></span></span><br />
<div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 6. Second order, low-pass 20 MHz Butterworth Sallen-Key filter.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The OPA695 implementation hits the desired maximally flat Butterworth design with a 20 MHz cutoff almost exactly. The OPA820 placed into the same circuit shows a slight peaking and reduced bandwidth as predicted. This performance contrasts with the MFB filter discussed in Part 1 of this article, where a VFB is preferred and the effect of finite amplifier gain bandwidth product (GBP) moves the actual poles on a constant 0 circle to lower Q.</span></span><br />
<br />
<b><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Example D</span></span></b><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Where the gain needs to be adjusted, a CFB amplifier is preferred because it holds more constant bandwidth as that adjustment is made. Figure 7 shows an example non-inverting design where the adjustment is configured to provide a fine-scale tune from a gain of +2 to +4 V/V using a high output current OPA691.</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjD0v3ReygCFDTqIjMMY6KdDEHy9q5hyjY2WEeRN5HubuRn6Hv5ZBletx96XpQQfs4H3cmsIIsifdQLwlVqJJdmYkxUqMKq8C8h_oPkniuDg6IjzTKUGee6Paz3MxlJ7Rm4mYIcZuzkOHc/s1600/C0154p2-Figure7.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="306" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjD0v3ReygCFDTqIjMMY6KdDEHy9q5hyjY2WEeRN5HubuRn6Hv5ZBletx96XpQQfs4H3cmsIIsifdQLwlVqJJdmYkxUqMKq8C8h_oPkniuDg6IjzTKUGee6Paz3MxlJ7Rm4mYIcZuzkOHc/s400/C0154p2-Figure7.jpg" width="400" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 7. Adjustable gain using the high output current OPA691.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">In all of these CFB circuits, the feedback resistor is selected and fixed near the recommended value for that particular CFB device. Any adjustments or frequency response shaping is then done using only the gain element.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Since the loop gain does not depend strongly on the signal gain, this type of adjustment holds a more constant bandwidth using a CFB as opposed to a VFB implementation. Conversely, this circuit with the gain adjustment in the feedback resistor would have a significant frequency response variation when using a CFB.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">To compare, Figure 8 shows the circuit of Figure 7 simulated at the gain extremes using both the CFB OPA691 and a very similar VFB device, the OPA690.</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgQmYtZSBV1nH7pN9jyBWkI5AJCjCfk-ASbgR2m-TgM3Dnado6DWHX1JXaUTlgDz65qSUPbX_fW3FMQdjY8fAbVcKQ75Kdwy5UQrIB-3bWeDDXwopL1mOxoivDt8QWBLyKMu-aUe3Hk8fE/s1600/C0154p2-Figure8.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgQmYtZSBV1nH7pN9jyBWkI5AJCjCfk-ASbgR2m-TgM3Dnado6DWHX1JXaUTlgDz65qSUPbX_fW3FMQdjY8fAbVcKQ75Kdwy5UQrIB-3bWeDDXwopL1mOxoivDt8QWBLyKMu-aUe3Hk8fE/s320/C0154p2-Figure8.jpg" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 8. Adjustable gain small-signal bandwidth comparison.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">At a gain of +2 V/V (6 dB), both parts show about the same bandwidth (280 MHz) where the OPA691 is closer to a Butterworth response while the OPA690 is bit more peaked. Adjusted to a gain of +4 V/V (12 dB), the OPA691 still holds >220 MHz bandwidth while the OPA690 drops to around 100 MHz.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Most simple circuits not mentioned thus far can generally use either a VFB or CFB device. It is sometimes suggested that some of these circuits cannot be implemented using a CFB device; this claim is often incorrect. One example that demonstrates this is the differencing amplifier.</span></span><br />
<br />
<b><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Example E</span></span></b><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">A single amplifier differential stage (sometimes called a 'differencing' amplifier) can use either VFB or CFB devices. The common-mode rejection ratio (CMRR) of a CFB implementation appears to be lower when compared to an equivalent VFB design. However, that CMRR is the effect of the buffer gain loss across the input stage and is quite repeatable for a particular CFB part number. It is possible to tune up the CMRR to a much higher dc level for a CFB differencing amplifier by slightly increasing the resistor to ground on the non-inverting input.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 9 shows a representative differencing amplifier using the very high slew rate, unity gain stable, VFB OPA690. Notice also that the resistors on the non-inverting side were adjusted down to achieve a matched input impedance for each source (if V1 and V2 are independent sources. See Reference 1 for an example of where they are not).</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhWsxX0l8Ca1ejLWPS9va6uuFbFackYa0gZQNWV0Iz9Hp7LNdmqVW44ZGG8ZVm92Pw9OmO_lALFgD9AfeRHQEpKmCtaIXbDSRerPadynMsaqWxqjZ0H6MsXHDT4jmB6TrscY_wxQUkvRE/s1600/C0154p2-Figure9.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="155" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjhWsxX0l8Ca1ejLWPS9va6uuFbFackYa0gZQNWV0Iz9Hp7LNdmqVW44ZGG8ZVm92Pw9OmO_lALFgD9AfeRHQEpKmCtaIXbDSRerPadynMsaqWxqjZ0H6MsXHDT4jmB6TrscY_wxQUkvRE/s400/C0154p2-Figure9.jpg" width="400" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 9. Wideband differencing amplifier using an OPA690.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">A series resistor into the non-inverting input is then added to achieve bias current cancellation, which would only work to improve output offset voltage in a VFB implementation. This is assuming 0 Ω sources for each source and two independent sources.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">This same circuit can be built using the CFB OPA691. Figure 10 shows a CMRR simulation where both inputs are tied together and driven.</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjH49frcFRobARSODDslN_GOrl1YS-62IkdDX9sNfpUFYLahioO-Ie3ZL8Sf5f1br6E87JfMFO846D7-N23JpgKl-PhYCy8ghE1CpIa_G3zixiIvlXQF_N9nSb_KR1qETmoF_Xm_UOg5ks/s1600/C0154p2-Figure10.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjH49frcFRobARSODDslN_GOrl1YS-62IkdDX9sNfpUFYLahioO-Ie3ZL8Sf5f1br6E87JfMFO846D7-N23JpgKl-PhYCy8ghE1CpIa_G3zixiIvlXQF_N9nSb_KR1qETmoF_Xm_UOg5ks/s320/C0154p2-Figure10.jpg" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 10. CMRR simulation for OPA690 and OPA691.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The resulting small output gain (large negative dB gain) is then input-referred and the negative taken to get a typical CMRR plot. The OPA690 shows slightly higher CMRR than the OPA691. In this case, the resistors of Figure 9 have been used in both simulations, and no adjustment for improved CMRR made in the OPA691 simulation.</span></span><br />
<br />
<b><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Differential input/output circuits</span></span></b><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">An emerging class of amplifiers called fully differential amplifiers (FDA) easily can take a single or differential input signal. and produce a differential output centered on a user-selected common-mode operation point. An alternative approach in going differential-in to differential-out has been to use standard dual op amps. A brief review of that approach helps to set the background for the FDA. These approaches are useful also because once they are understood, they open up a large range of dual op amps to the designer for possible application.</span></span><br />
<br />
<b><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Application A</span></span></b><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Differential I/O circuits can be easily implemented using either a VFB or CFB. There is, however, some difference between a non-inverting or inverting input implementation with regard to how the common-mode voltage is treated. In the non-inverting input case, the two inputs show a high input impedance to the differential source (allowing filters or other passive circuits to be easily inserted up to these inputs). The common-mode gain from the non-inverting inputs to the differential outputs will be one.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 11 shows an example of this design where the wideband, high output current, dual OPA2614 is used to implement a DSL driver.</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"></span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiPXrTwq-WIpsnTQN07sZJqXglByeZTRrcVYPklkKy-IAH30U9mFgrZVXnPQ9PhZiBimrxRnHB9Ptg5neHI6kUrz3yJ3PBLlnpciJPZwPIma4WmH8dxkf2yB7QU6fnJhVcKbgX0WUEQ3_s/s1600/C0154p2-Figure11.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="260" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiPXrTwq-WIpsnTQN07sZJqXglByeZTRrcVYPklkKy-IAH30U9mFgrZVXnPQ9PhZiBimrxRnHB9Ptg5neHI6kUrz3yJ3PBLlnpciJPZwPIma4WmH8dxkf2yB7QU6fnJhVcKbgX0WUEQ3_s/s400/C0154p2-Figure11.jpg" width="400" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 11. Non-inverting differential I/O circuit using the OPA2614.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Here, the amplifier operates on a single +12 V supply and the filtered differential source is driven through blocking capacitors to the mid-supply referenced termination impedance. The differential gain is set to 6 V/V with a dc blocking capacitor in series with the gain resistor to further attenuate low-frequency noise and reduce output differential offset voltage.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Whether that capacitor is present in the circuit or not, the mid-supply reference on each non-inverting input shows up as the output common mode voltage as well. This circuit demonstrates a typical 1:2 step-up transformer at the output to a 100 Ω load, giving a nominal differential load of 50 ohms.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">This circuit is often implemented using dual current feedback op amps (such as the OPA2677) but can give lower output noise using a decompensated dual voltage feedback op amp (for example, the OPA2614). Figure 12 shows the simulated frequency response for this circuit showing about 50 MHz bandwidth—more than adequate for most DSL line driver applications.</span></span><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhuXfbrUgTP-XL90-UQd312DuhH-dEntJgxfjCpTQGdnPNsWpS699_oIfvgI9yKDKiix3wOinXI-A720ABaVHesIkS5ALR30ssGH0XX7hSSibTDVWDPlTfA8eUT1bqW6jiesnwBb-QophA/s1600/C0154p2-Figure12.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhuXfbrUgTP-XL90-UQd312DuhH-dEntJgxfjCpTQGdnPNsWpS699_oIfvgI9yKDKiix3wOinXI-A720ABaVHesIkS5ALR30ssGH0XX7hSSibTDVWDPlTfA8eUT1bqW6jiesnwBb-QophA/s320/C0154p2-Figure12.jpg" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 12. Non-inverting differential I/O small-signal frequency response.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">In the inverting input, differential I/O implementation, the differential input impedance is the sum of the two gain resistors; the output common-mode voltage depends on the dc voltage applied to the non-inverting inputs and the dc gain for that signal path, along with the dc common-mode voltage of the source. If the sources are capacitively or transformer-coupled, the common-mode voltage applied to the non-inverting inputs will have a gain of one to the output.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 13 shows an inverting differential I/O using the very low power OPA2684 dual CFB in a single +5 V supply with a mid-supply common-mode reference and an ac-coupled input interface.</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"></span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj7u-kerQu4Jg_gOChksECHDORZPUckVtJMzY4Aq_0fRAbzJBVf8R2szAivg3-AGSPAe3YjaEj0udJFKpowvwIBNKsTWOpR2rNjZBPKMwHxG3zmo5vMvv1IUw77omNf4r6mRtLYe6RKXMM/s1600/C0154p2-Figure13.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="223" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj7u-kerQu4Jg_gOChksECHDORZPUckVtJMzY4Aq_0fRAbzJBVf8R2szAivg3-AGSPAe3YjaEj0udJFKpowvwIBNKsTWOpR2rNjZBPKMwHxG3zmo5vMvv1IUw77omNf4r6mRtLYe6RKXMM/s400/C0154p2-Figure13.jpg" width="400" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 13. Low power, inverting differential I/O using the OPA2684.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">This circuit provides a common-mode output of 2.5 V with a differential gain of five and >100 MHz bandwidth while using only 3.6 mA total quiescent supply current.</span></span></div><div style="text-align: justify;"><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 13 also shows a differential ac input impedance of 400 ohms. One advantage of the OPA2684 is that the source impedance (possibly a filter) will not interact with the amplifier bandwidth. A dual VFB amplifier used here will work, but the source impedance would then be part of the loop gain equation and might adversely impact the frequency response.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 14 illustrates a simulation of this low-power inverting input differential I/O example where a dual VFB device, the OPA2822, is also shown.</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEisEbQc8YI1j3p9H2TGnXriSfoYdQpLJynD4wkVS6WY-t2sNQKRA6qLkbn6ay9nw0Buhyphenhyphen8OSDG1Il5rEaUG3oMYqen7I3jHwy4RKP7URLSUXAlRXwbVgo_h9yCAp9Ye31HAwdwC51XMQgU/s1600/C0154p2-Figure14.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEisEbQc8YI1j3p9H2TGnXriSfoYdQpLJynD4wkVS6WY-t2sNQKRA6qLkbn6ay9nw0Buhyphenhyphen8OSDG1Il5rEaUG3oMYqen7I3jHwy4RKP7URLSUXAlRXwbVgo_h9yCAp9Ye31HAwdwC51XMQgU/s320/C0154p2-Figure14.jpg" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 14. Inverting input differential I/O frequency response.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">That part is a unity gain stable, 200 MHz GBP device so this noise gain of six configuration shows about 35 MHz bandwidth versus >150 MHz bandwidth for the OPA2684.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Fully differential amplifiers are essentially VFB devices with an added output common-mode control loop. Instead of an internal differential to single-ended conversion, such as standard op amps require, these devices continue the signal path to the output differentially. All of the applications discussed in Part 1 for VFB devices would also be suitable for an FDA device adapted to a differential signal path. However, there are at least two types of application circuits where the FDA provides a compelling solution as compared to standard VFB implementations.</span></span><br />
<br />
<b><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Application B</span></span></b><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">A dc-coupled, single-ended input to differential output with output common-mode control can best be implemented with an FDA device. One of the key considerations in this design is to match the feedback divider ratios on each side of the FDA circuit, including the signal source impedance. It is also important to understand that the common-mode control loop is level-shifted from the input to the output by setting up a common-mode current in the feedback paths. Therefore, the source must be able to sink or source a portion of this dc common-mode current. (See Reference 2 for a discussion of basic FDA operation and applications.)</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 15 shows an example circuit using the THS4511, a very wideband, single, 5V-supply FDA that includes ground in its input common-mode range.</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"></span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhE2CgA1aasUJOEaj9pLisf5Jf1wm4t2uUeL0tXUFDGZx0kBAheMp1rSe0YWejzt2YlG4WDlxYkFA5veGGWYR-9UXIijPW1a1F1FAKSTOXC0B4epDAa3H3Fk6kfKyPyWxslZtQW8EkEOV4/s1600/C0154p2-Figure15.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="158" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhE2CgA1aasUJOEaj9pLisf5Jf1wm4t2uUeL0tXUFDGZx0kBAheMp1rSe0YWejzt2YlG4WDlxYkFA5veGGWYR-9UXIijPW1a1F1FAKSTOXC0B4epDAa3H3Fk6kfKyPyWxslZtQW8EkEOV4/s400/C0154p2-Figure15.jpg" width="400" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 15. Single-ended input to differential output using the THS4511.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">This feature makes the THS4511 particularly useful for converting a single-ended, ground-referenced signal that swings only above ground into a differential output around a common-mode voltage.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The THS4511 shows a very high full-power bandwidth with its 2 GHz GBP and 4900 V/μsec differential slew rate. These two characteristics together give an exceptional pulse response in a dc-coupled single to differential conversion. Figure 16 shows the simulated frequency response.</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgNCCcBlB7EUhSR2bZ-eGZ2dLDJuXXJGLyjh1aGcN0onz2BZlO1XLB0qy5Yjg1P9til1QF5U_NglussAfErr8b-QHcilhCVdbODEDjZdIidU9H3ZTzmeicUSgY3JxWckVkBavtTrlSBZWk/s1600/C0154p2-Figure16.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgNCCcBlB7EUhSR2bZ-eGZ2dLDJuXXJGLyjh1aGcN0onz2BZlO1XLB0qy5Yjg1P9til1QF5U_NglussAfErr8b-QHcilhCVdbODEDjZdIidU9H3ZTzmeicUSgY3JxWckVkBavtTrlSBZWk/s320/C0154p2-Figure16.jpg" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 16. DC-coupled single to differential frequency response.</span></span></div><br />
<b><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Application C</span></span></b><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Differential-input-to-differential-output circuits with very low distortion can clearly benefit from the FDA topology. Where a low IF requirement needs the best third-order intermodulation spurious suppression using modest quiescent power levels, a transformer-coupled FDA implementation provides a surprisingly low-noise figure with exceptionally low harmonics.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 17 shows an example of this type of circuit using the very wideband THS4509.</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"></span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgVp1q4VJRgTQjagcxRLXwG0Qpr_ZsA_Tltko38wvUYFeNZL8TRiPvp-nNjuRjTa0BhJa1Pm7w3iPxVxQoTZwAF2akRepAUs7xAettnw7_z8pUSahJhZtN5g8uod9yI5NkV9bfR2gWK90Q/s1600/C0154p2-Figure17.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="152" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgVp1q4VJRgTQjagcxRLXwG0Qpr_ZsA_Tltko38wvUYFeNZL8TRiPvp-nNjuRjTa0BhJa1Pm7w3iPxVxQoTZwAF2akRepAUs7xAettnw7_z8pUSahJhZtN5g8uod9yI5NkV9bfR2gWK90Q/s400/C0154p2-Figure17.jpg" width="400" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 17. Very low noise and distortion IF amplifier using the THS4509.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">This example gives a noise figure of 8.2 dB (from a 50 Ω source) while also giving >100 dB two-tone spurious free dynamic range (SFDR) through 70 MHz for 2 Vpp outputs. This performance is equivalent to a 54 dBm third-order intercept in an FDA using approximately 200 mW quiescent power.</span></span><br />
<br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">The 1:1.4 input turns-ratio transformer reflects the 100 Ω differential input impedance of the FDA circuit to a 50 Ω termination (Reference 3 discusses this circuit and measured performance in detail). In this case, the transformer becomes the bandwidth limiting element. Figure 18 shows the simulated performance, including the transformer model.</span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"></span></span><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;"> </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgNc6MKaD7AbFDUcXbMCL_SMi2Ui5uSN_Y3QAnw0DNIHZntRi4CI1yomXL7qeMBILBVYSuoAmbCFanMjbwqzvq-1ZFGaVnnT1x4_3Ix7ZAxDLZE_vMYkINjFJWILn7WIf6sMcs10oMZfYY/s1600/C0154p2-Figure18.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgNc6MKaD7AbFDUcXbMCL_SMi2Ui5uSN_Y3QAnw0DNIHZntRi4CI1yomXL7qeMBILBVYSuoAmbCFanMjbwqzvq-1ZFGaVnnT1x4_3Ix7ZAxDLZE_vMYkINjFJWILn7WIf6sMcs10oMZfYY/s320/C0154p2-Figure18.jpg" /></a></div><div style="text-align: justify;"><div style="text-align: center;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Figure 18. Small-signal bandwidth for the transformer-coupled FDA.</span></span></div><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">This single to differential gain of 7 V/V shows up as a low frequency gain of 16.9 dB. The first rolloff above is the transformer while the second break in the rolloff curve is the appearance of the THS4509 bandwidth limitation. As can be seen, this circuit gives very good flatness through 200 MHz IF frequencies.</span></span><br />
<br />
<b><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Conclusions</span></span></b><br />
<span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Today's circuit designers enjoy a tremendous selection of high performance wideband op amps. Newer and increasingly better devices are emerging steadily, showing constant improvement on the speed versus power tradeoff. Where the feedback element needs to be adjustable or is capacitive, a voltage feedback or fully differential device is the preferred solution. Where gain flexibility or frequency response shaping is desired in a low-power implementation, and dc precision is a secondary concern, a current feedback device would be the first choice. Many applications can use either a VFB or CFB device where issues such as the speed/power tradeoff, noise or dc precision become the deciding factor.</span></span></div><div style="text-align: justify;"><br />
</div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">Hernández Caballero Indiana<br />
Asignatura: CAF<br />
Fuente:<a href="http://www.planetanalog.com/features/showArticle.jhtml;jsessionid=NLLCHX2JOWNJUQSNDLPCKH0CJUNN2JVN?articleID=196702013">http://www.planetanalog.com/features/showArticle.jhtml;jsessionid=NLLCHX2JOWNJUQSNDLPCKH0CJUNN2JVN?articleID=196702013</a></span></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-56901426772915528682010-06-26T19:20:00.002-04:302010-06-27T19:22:55.191-04:30Application basics when using wideband voltage and current feedback op amps, Part 1 (of 2)<div class="post-header"></div><div class="post-body entry-content"><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_filelist.xml" rel="File-List"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_themedata.thmx" rel="themeData"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_colorschememapping.xml" rel="colorSchemeMapping"></link> <style>
<!-- /* Font Definitions */ @font-face {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4; mso-font-charset:0; mso-generic-font-family:roman; mso-font-pitch:variable; mso-font-signature:-1610611985 1107304683 0 0 159 0;} @font-face {font-family:Calibri; panose-1:2 15 5 2 2 2 4 3 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:-1610611985 1073750139 0 0 159 0;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {mso-style-unhide:no; mso-style-qformat:yes; mso-style-parent:""; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:0cm; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoPapDefault {mso-style-type:export-only; margin-bottom:10.0pt; line-height:115%;} @page Section1 {size:612.0pt 792.0pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} -->
</style> <br />
<div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"> </span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">Understand the basics of current and voltage feedback op amps and where they fit, along with constraints and implications</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">With both current and voltage feedback operational amplifiers (op amps) available to the system designer, how do you select which device to use? This two-part article discusses applications most suited to each type of op amp, and why certain applications are unsuitable for one or the other type of amplifier. Widely-used circuits are shown with example designs. The emerging fully differential amplifier type of amplifier (a special case of a voltage feedback device) is also shown along with several suitable applications. Part 1 reviews the internal differences between the two types of op amps and presents some key applications most suitable to voltage feedback type devices.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><b>Initial amplifier selection criteria</b></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">There is a bewildering array of possible op amps for a designer to select from in any given application. However, there are distinct internal differences between the two major types of amplifiers: voltage feedback (VFB) and current feedback (CFB). These differences may lead a designer to choose one over the other in certain applications. A newer type of op amp, the fully differential amplifier (FDA), is a type of voltage-feedback op amp that includes an output common-mode control loop. It has the same application emphasis as a standard voltage feedback amplifier, as well as several specific applications ideally suited to this type of amplifier.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">Before giving any attention to the type of amplifier to use, most designers first should consider the output signal requirements (for example, maximum desired output Vpp and output current, as well as load type) and necessary dynamic characteristics such as settling time, full power bandwidth, or a distortion requirement. Using these specifications, the universe of possible amplifiers can be narrowed to devices that can handle the correct range of supply voltages needed to deliver the output Vpp, and then limited further to a minimum supply current versus desired output dynamic characteristic. Normally, a CFB gives the best power efficiency for higher-frequency dynamic range needs, while a VFB generally has better noise and/or DC precision, and is the part of choice for certain types of circuits.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><b>Internal comparison of voltage and current feedback op amps</b></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">To understand why some circuits work better with one or the other type of amplifier, you need to first understand the internal topology of each amplifier and their resulting transfer functions. Compare a simplified expression for the Laplace transfer function written in loop gain format. Figure 1 shows the internal block diagram of a VFB along with the internal model and closed loop transfer function. A(s) is the frequency-dependent open-loop gain of the op amp. It is modeled here as a single dominant pole response. Figure 1 uses an inverting gain configuration for comparison purposes because the FDA device is most clearly understood as a differential inverting configuration.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj8hYgPbLomJHAzJnhIJRmNgUIf2zwms-ZHmmlrV5EwAy76hRcoH_JIG0LMKeNqCqIzJRBVFNg9CiTKdxUhmSBaSX1fTgWyW8yUXMwV5XzF6-STnzOt1XgI9KeeHSine5own6Y1b_Oq6Ug/s1600/C0154-Figure1.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="220" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj8hYgPbLomJHAzJnhIJRmNgUIf2zwms-ZHmmlrV5EwAy76hRcoH_JIG0LMKeNqCqIzJRBVFNg9CiTKdxUhmSBaSX1fTgWyW8yUXMwV5XzF6-STnzOt1XgI9KeeHSine5own6Y1b_Oq6Ug/s400/C0154-Figure1.jpg" width="400" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 1. Open loop to closed loop conversion for voltage feedback.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">The transfer function has the desired gain in the numerator (-RF/RG) and a loop gain (LG) term in the denominator that determines the frequency response. One way to understand this LG is to plot [20 · Log (A(s))] and [20 · Log(1+RF/RG)] on the same grid. The key issues for this plot are: 1) the separation between these two curves at lower frequencies (this separation shows the magnitude of the loop gain); and 2) at what frequency they intersect.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">At the point of intersection, sometimes called loop gain crossover, the term in the denominator of the transfer function drops to 1 + 1e-jθ (where jθ is the angle of that expression). The important check is that this angle is well away from -180 degrees to avoid closed loop oscillations or peaking. Figure 2 shows an example loop-gain plot of these two terms, where a simple single-pole response for A(s) is assumed and no phase added by the feedback network.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg6c0otK31AErXUrjuCxvO9R_JvJUYsr2dXxdkH_cSVpfZBqVQVhkFwpB1XrFfXOI2oP1UgZmB4jAaCIDcj6V2XC1p0E-5_Hib81uSu6ntnOaE9Dq2tq1i2-NBQyQDTt6GE3dmFF2iIY9Q/s1600/C0154-Figure2.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg6c0otK31AErXUrjuCxvO9R_JvJUYsr2dXxdkH_cSVpfZBqVQVhkFwpB1XrFfXOI2oP1UgZmB4jAaCIDcj6V2XC1p0E-5_Hib81uSu6ntnOaE9Dq2tq1i2-NBQyQDTt6GE3dmFF2iIY9Q/s320/C0154-Figure2.jpg" width="316" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 2. Loop gain and phase for a VFB op amp. X-axis is log frequency.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">In Figure 2, the (1 + RF/RG) term is assumed to add no phase impact to the loop gain; only the open-loop phase of A(s) introduces loop phase shift in this simple example. This graph is the lower plot, where the loop gain crossover frequency is mapped down to find the remaining phase margin at that frequency.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">Note that it is impossible for the VFB to change the signal gain without changing the loop-gain characteristic. This effect is where the gain bandwidth product (GBP) concept arises. If the gain increases, the bandwidth must decrease. If the gain decreases, the bandwidth increases, and the phase margin will normally decrease. (See Reference 1 for a more complete discussion.)</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">In contrast, the internal workings of a CFB op amp are quite different. Those blocks and the resulting closed loop transfer function for the inverting configuration are shown in Figure 3 where, again, an inverting configuration is used and a single pole internal transimpedance gain is assumed for Z(s).</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_NLE3_8ItREPVh7ydgFfkT74OXoE4mNH6Z5CuckJB1LcHIGu55PHE6ipaLWSNPEZpofxgVYD84u6FxIvf5xtbbicgjXWYgZDzk3twF_-TqpHBqoJ9l6vrzfaY3yHopJjrl38r7v0C9pM/s1600/C0154-Figure3.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="170" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_NLE3_8ItREPVh7ydgFfkT74OXoE4mNH6Z5CuckJB1LcHIGu55PHE6ipaLWSNPEZpofxgVYD84u6FxIvf5xtbbicgjXWYgZDzk3twF_-TqpHBqoJ9l6vrzfaY3yHopJjrl38r7v0C9pM/s400/C0154-Figure3.jpg" width="400" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 3. Current feedback internal structure and closed loop response.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">The CFB uses a unity-gain buffer across the two inputs. This forces the inverting node voltage to follow the non-inverting input voltage. That buffer is intended to present a low impedance to the inverting port, where a low level error current may be sensed and passed on to the output through a transimpedance gain. It is this internal transimpedance gain, Z(s), which acts in the same fashion as the VFB A(s) to provide a high DC gain with a dominant pole.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">When the loop is closed, the same desired gain is achieved; but the loop-gain terms are very different. The CFB amplifier has a loop gain set by the forward transimpedance gain compared to the feedback impedance. Figure 4 plots the loop gain and phase for a typical CFB amplifier, where the feedback element is assumed to introduce no phase shift in this simplified analysis.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjY-VPdr8TLizVgvl1452v0pBhTInAzS5euzFqKM-43f2TfO6gOOId80dm8piEhoUZw0cECDJdR_QA3FHFWsSiepwUhvOZH9DLMgAn48k0C0d8ddhUUMJ8EUoDcKtxNbTSITmfz8OdRcnA/s1600/C0154-Figure4.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="320" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjY-VPdr8TLizVgvl1452v0pBhTInAzS5euzFqKM-43f2TfO6gOOId80dm8piEhoUZw0cECDJdR_QA3FHFWsSiepwUhvOZH9DLMgAn48k0C0d8ddhUUMJ8EUoDcKtxNbTSITmfz8OdRcnA/s320/C0154-Figure4.jpg" width="316" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 4. Current feedback (CFB) loop gain and phase plots. X-axis is log frequency.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">This plot looks very similar to the VFB plot except that the external element setting the loop gain is the feedback impedance alone. The greatest difference between the VFB and CFB amplifier is that the loop gain can be set separately from the signal gain using the feedback impedance. The feedback impedance becomes an independent compensation element, where the gain can then be set using the normal gain equations from whatever impedance value is selected for RF. This approach gives what is sometimes called gain bandwidth independence for the CFB amplifier. (See Reference 1 for a more detailed discussion.)</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">The final type of amplifier to be considered here is the new fully differential amplifier (FDA). Figure 5 shows the configuration and closed loop transfer function for this type of amplifier.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiNYZV7v1-wMJRlHDXRnnxvdFWT5tGx9W3r7d-Xym4XHLHHUBqao3kDEV5EgEtgixSLrfx-tXwG6S0XdoK4F84GL9R4l3QrxNRgzsnqzwCO8IPhvsR4MAK5k8Gd5bcP48TTr4rCeu1VNsA/s1600/C0154-Figure5.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiNYZV7v1-wMJRlHDXRnnxvdFWT5tGx9W3r7d-Xym4XHLHHUBqao3kDEV5EgEtgixSLrfx-tXwG6S0XdoK4F84GL9R4l3QrxNRgzsnqzwCO8IPhvsR4MAK5k8Gd5bcP48TTr4rCeu1VNsA/s400/C0154-Figure5.jpg" width="280" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 5. Fully differential amplifier (FDA) structure and transfer function.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">If the two feedback networks are allowed to be unmatched, the transfer function is fairly complicated. If they have a matched divider ratio (see Figure 5), the equations simplify to be the same as the inverting VFB transfer function. The effect of the separate common-mode loop is not shown. This loop acts to servo the average output voltage to a value set by a VOCM input pin voltage (see Reference 2 for a more complete discussion of the FDA topology). For applications considered in this article, the FDA is treated as differential VFB device.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><b>Application imperatives</b></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">In the range of possible applications for wideband op amps, several types must use VFB devices. These circuits can sometimes be forced to work using CFB devices, but usually at the cost of complexity and poorer performance. Any circuit that requires flexibility in the feedback element and/or capacitors in the feedback will have stability problems with a CFB device. This instability is the result of the loop gain depending on the feedback impedance. Therefore, any circuit that needs a lot of flexibility in that impedance is going to interact with the achievable frequency response if a CFB amplifier is used.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">The following example circuits should use a VFB device for implementation.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><b>A. Transimpedance amplifiers.</b> These circuits take a current source input, typically from a capacitive source, and turn it into a voltage at the output. The feedback resistor is the gain element and normally needs a compensation capacitor in parallel for correct operation. Figure 6 shows an example using the OPA657, a very wideband JFET input device uniquely suited to the transimpedance application. This device is a non-unity gain stable VFB with relatively low input noise voltage and very high gain bandwidth product. For a given diode source capacitance, the amplifier gain bandwidth product (GBP) determines the achievable bandwidth and/or transimpedance gain (Reference 3).</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjNomhnOXY1MPZ73_dIBCEHee5k4GhcJ0T8b9EjyQlQ6uTBVuYxfGAGk0ZuhqhoDbgxFgAwey5gR-_ogu4qBQ24EDPJeaiWRpjYTrJI4SVAolvCbf3zZcqp006IYhVUhRvERYNiZctjIQ0/s1600/C0154-Figure6.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="268" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjNomhnOXY1MPZ73_dIBCEHee5k4GhcJ0T8b9EjyQlQ6uTBVuYxfGAGk0ZuhqhoDbgxFgAwey5gR-_ogu4qBQ24EDPJeaiWRpjYTrJI4SVAolvCbf3zZcqp006IYhVUhRvERYNiZctjIQ0/s320/C0154-Figure6.jpg" width="320" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 6. Example transimpedance design using the OPA657.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">In this example, the 500 kΩ along with the 200 pF diode capacitance gives a noise gain zero at approximately 1.6 kHz. With the feedback capacitor set to achieve a maximally flat Butterworth response, the resulting F-3dB will be at the geometric mean of this zero and the 1.6 GHz gain bandwidth product of the OPA657. (Reference 3 gives a detailed analysis for compensation and noise in a transimpedance design.) Figure 7 shows the 1.6 MHz transimpedance bandwidth in a simulated frequency response of Figure 6.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnbUm6eohD9N6kU4RlJ2KPnszUWf4M6QzmkN3lnstMicUNVnJrVEYBjMIKmP2hMMfRbcLrDgn0_EY0SZdRwnwBIr-BAj846z1BL-8Ahlz9Vy9DfV2Aw8rJRQA16NRy6hQSbXAJrVfITFw/s1600/C0154-Figure7.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="232" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnbUm6eohD9N6kU4RlJ2KPnszUWf4M6QzmkN3lnstMicUNVnJrVEYBjMIKmP2hMMfRbcLrDgn0_EY0SZdRwnwBIr-BAj846z1BL-8Ahlz9Vy9DfV2Aw8rJRQA16NRy6hQSbXAJrVfITFw/s320/C0154-Figure7.jpg" width="320" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 7. Simulated transimpedance frequency response of Figure 6.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">B. Integrator based circuits. These applications are looking for a capacitive feedback to implement an integrator function. A good example would be the Multiple feedback (MFB) active filter. Figure 8 shows an example using the OPA820, a low-noise, wideband voltage feedback op amp uniquely suited to this application.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">Embedded within this filter circuit is an integrator configuration that arises from the 200 Ω and the 12.5 pF feedback capacitor.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">At very high frequencies, that capacitor shorts out, giving a local unity-gain feedback for the amplifier. This result suggests that a unity gain stable VFB should be used in this type of circuit to avoid high frequency oscillations. This particular example is targeting a 10 MHz low-pass Butterworth response with an in-band gain of -4 V/V. (Reference 4 describes how to choose the R's and C's in the MFB filter for improved noise and distortion.)</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh9QzMFItyW5g55hsbn41TaoKHD2aoQTI7Y_EJ8JYDIJLPNPLP4IlCr7OMdAQKEm5meko__eGpRLWGE5piM1JG-yMTPQoyJqP9b6I1ca4R_VIWBptSyAyFoKg13ws3j9vTbhtjYgt-DjpQ/s1600/C0154-Figure8.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="215" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh9QzMFItyW5g55hsbn41TaoKHD2aoQTI7Y_EJ8JYDIJLPNPLP4IlCr7OMdAQKEm5meko__eGpRLWGE5piM1JG-yMTPQoyJqP9b6I1ca4R_VIWBptSyAyFoKg13ws3j9vTbhtjYgt-DjpQ/s400/C0154-Figure8.jpg" width="400" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 8. Example MFB filter using the OPA820.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">Since the local feedback capacitor shorts out at higher frequencies, this circuit normally needs to use a unity gain stable VFB. (Reference 4 suggests a path to improved phase margin in this circuit using non-unity gain stable amplifiers.) One of the advantages of the MFB design is improved stopband rejection (over the Sallen-Key filter), and very good filter accuracy versus finite amplifier gain bandwidth product. This filter tends to achieve a slightly lower Q than that targeted as the Ω0 moves closer to the amplifier GBP.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjMmyIdH2E5bNPIOJIxbSbkrJoze7kLdj9FRMYi3Mxl-JI6eqlev5eOBMyevAPWRkGbcvNFFG-X-bT4FxQjPxLoGZdZqiw5I3l-3AZ9MEJ7ZvHRqEc5bxUT15bS6iP3RLqZADMTacdeu_Y/s1600/C0154-Figure9.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="234" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjMmyIdH2E5bNPIOJIxbSbkrJoze7kLdj9FRMYi3Mxl-JI6eqlev5eOBMyevAPWRkGbcvNFFG-X-bT4FxQjPxLoGZdZqiw5I3l-3AZ9MEJ7ZvHRqEc5bxUT15bS6iP3RLqZADMTacdeu_Y/s320/C0154-Figure9.jpg" width="320" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 9. Simulated 10 MHz Butterworth filter of Figure 8.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">C. Circuits with simple feedback poles implemented as an RC in the feedback network. Designers often implement a low-pass pole in this fashion. Since the feedback impedance is now a parallel RC network, this circuit must be implemented with a VFB, and preferably a unity-gain stable VFB. This type of simple filtering works best for inverting signal paths. In that case, the input signal sees the gain resistor as an input impedance that converts the signal to a current into the inverting node. From there, it continues into the feedback impedance to set the gain to the output.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">This type of pole implemented for a noninverting configuration has a pole/zero pair because the gain transitions from a DC value set by the resistors to unity gain as the feedback capacitor shorts out at higher frequencies. Therefore, this circuit drops to unity gain if implemented as a non-inverting stage. In the inverting configuration, the gain continues down with a one pole response. It is important to notice that a unity-gain stable amplifier would be preferred because the noise gain drops to unity for either the inverting or non-inverting application.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">Figure 10 shows an example using the THS4281 (a low-power, rail-to-rail output VFB) in the inverting configuration. In this example, the signal path was AC-coupled through a blocking capacitor. This allowed the non-inverting bias voltage to be set to mid-supply and then have a DC gain of one to the output. Because the THS4281 includes the negative rail on the input, an alternative DC-coupled design is possible by changing the lower 8 kΩ resistor on the non-inverting input to 889 Ω and removing the input blocking capacitor.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">This AC-coupled design allows a direct comparison of this circuit to a low-power CFB that does not have an input range extending to ground. That device, the OPA684, also uses less than 2 mA supply current and gives greater than 100 MHz bandwidth in most applications. Figure 11 compares the simulated response of this 1 MHz one pole rolloff circuit of Figure 10, using both the THS4281 and the OPA684 (where the OPA684 would use a single +5 V supply). Both parts give the expected one pole rolloff, but the OPA684 shows a very anomalous response at higher frequencies indicative of probable oscillations.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjY9rGRYOydadt6edt1cHJyv7wSyMWc7hxUPhjjrW64DINA-JIC81nsB03BoswTIRV40cDKGQpztSCw94Ot8d1OI4rZjKPr2UQ1Bh4ngqGIZhhryQqDm6lTvTi7OAZ2O1WF8LIJBiGqYkY/s1600/C0154-Figure10.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="213" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjY9rGRYOydadt6edt1cHJyv7wSyMWc7hxUPhjjrW64DINA-JIC81nsB03BoswTIRV40cDKGQpztSCw94Ot8d1OI4rZjKPr2UQ1Bh4ngqGIZhhryQqDm6lTvTi7OAZ2O1WF8LIJBiGqYkY/s400/C0154-Figure10.jpg" width="400" /></a></div><span style="font-size: small;"><br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 10. Inverting band-limited design using the THS4281.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjduW0vCDGe9bgZIqfGu3xLGEovtSlQf0pgciaIC8ET_tZvtbMNnBbYeZfyTFk0MnFtiZg9uYTRT6SkCVgRj-3qijHHZZ3zNQN2GEL65jnXwzplcynSahctwlzL3cGeQ9dWMVZc5l2WhQ4/s1600/C0154-Figure11.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="234" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjduW0vCDGe9bgZIqfGu3xLGEovtSlQf0pgciaIC8ET_tZvtbMNnBbYeZfyTFk0MnFtiZg9uYTRT6SkCVgRj-3qijHHZZ3zNQN2GEL65jnXwzplcynSahctwlzL3cGeQ9dWMVZc5l2WhQ4/s320/C0154-Figure11.jpg" width="320" /></a></div><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 11. Simulated inverting low pass filter design.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">D. Wideband DC-coupled amplifiers with good DC precision. VFB op amps have better input offset voltage and (for bipolar amplifiers) matched input-bias currents. As a result, considerably lower output DC-offset voltage and drift can be delivered as compared to equivalent CFB implementations. This consideration becomes more important as the required gain increases. Figure 12 shows an example high gain, DC-coupled inverting amplifier stage using a non-unity gain stable VFB. The OPA846 offers very good input offset voltage and offset current along with a low 1.2 nV/√Hz input voltage noise.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">To take advantage of this low noise, the gain of -20 circuit in Figure 12 implements a matched 50 Ω input impedance using only the input resistor and then a 1 kΩ feedback resistor. If a 50 Ω DC-coupled source impedance is assumed, the required bias current cancellation resistor on the non-inverting input would be 100 Ω| in parallel with 1 kΩ = 90.9 Ω. Decouple this resistor with a parallel capacitor to reduce its high-frequency noise contribution.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">Another interesting aspect of this circuit is the noise gain (NG), which is also the gain for the input offset voltage, is reduced below the inverting signal gain because of the 50 Ω source resistor. Including that value in the NG equation gives an NG = 11 while the signal gain will be -20.<br />
</span></div><br />
<div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjd2X1GRVHXrXI66KDwvg9wMqSdOgGT3YR4OABLVTbHBkiY7pxvh-iX4lAk6gV3bo3_8-YkAGB0IfHeFbmGAj1mK0FE6Apv4ZxMXxvB0FUeubC5DRReNfVuI8b4ve0WYL3HfXxIfbHzp8k/s1600/C0154-Figure12.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="131" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjd2X1GRVHXrXI66KDwvg9wMqSdOgGT3YR4OABLVTbHBkiY7pxvh-iX4lAk6gV3bo3_8-YkAGB0IfHeFbmGAj1mK0FE6Apv4ZxMXxvB0FUeubC5DRReNfVuI8b4ve0WYL3HfXxIfbHzp8k/s400/C0154-Figure12.jpg" width="400" /></a></div><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 12. Inverting gain of -20, low-output Vos design, using the OPA846.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">This high-gain inverting implementation using the OPA846 can also be done using a low-power current feedback amplifier. For comparison, an OPA684 low-power CFB is compared in Figure 13 for the simulated frequency response. Since high equivalent gain bandwidth is a natural advantage for CFB amplifiers, the OPA684 gives very similar small signal bandwidth to the OPA846 of approximately 150 MHz. The OPA684 uses 1.8 mA quiescent current while the OPA846 uses 12.9 mA.<br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg0zX13r-B1BLJfJbzEn5_7BlMz7L8oVdQCuN8Oz9NKZYUDwkjkoYJp7D2ibvlJ4n_By7qfcJUORuNkFqNxyzj_D8FSEVEzqLGwm9SlJ81kwJYfNEIJQ_5REaclNO6BOFDaz89eD8xMMAU/s1600/C0154-Figure13.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="235" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg0zX13r-B1BLJfJbzEn5_7BlMz7L8oVdQCuN8Oz9NKZYUDwkjkoYJp7D2ibvlJ4n_By7qfcJUORuNkFqNxyzj_D8FSEVEzqLGwm9SlJ81kwJYfNEIJQ_5REaclNO6BOFDaz89eD8xMMAU/s320/C0154-Figure13.jpg" width="320" /></a></div><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: center;"><span style="font-size: small;">Figure 13. Gain of -20V/V simulated performance using VFB and CFB devices.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">A calculation of the maximum output DC offset error band at 25 °C for the OPA684 shows the relatively poor DC precision offered by the CFB implementation. That calculation must treat the two input bias currents separately, because they are not physically related in the CFB input stage as they are in most VFB input stages. Leaving the 90.9 Ω resistor on the non-inverting input, the total output DC error band, using the OPA684 specified maximum DC errors at 25 °C, is:</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">Maximum Vos =</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">±3.5 mV·11 V/V±10μA·91 Ω·11 V/V± 16μA·1 kΩ =</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">±64.5 mV</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">So, while the OPA684 can match the speed of the OPA846 in this higher gain application, if output DC precision (or lower noise) is desired, the VFB design offers considerable advantages.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><b>Conclusions to Part 1</b></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div style="text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;">In Part 1, we reviewed the key internal differences between VFB and CFB op amps as a means of identifying applications that must use the VFB topology over the CFB devices. These examples generally fall into two categories: applications that need a capacitive feedback for some reason; and circuits that need to emphasize DC precision and/or the lowest output noise. Part 2 will continue with applications uniquely suited to the CFB topology, and then introduce the newest member of the wideband op amp universe—the fully differential amplifier. Part 2 will conclude with illustrations of a few applications uniquely suited to this amplifier</span></div><div style="text-align: justify;"><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Hernández Caballero Indiana<br />
Asignatura: CAF<br />
Fuente:<a href="http://embedded.com/design/196701711">http://embedded.com/design/196701711</a> </span></div></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-37175585717408140052010-06-25T20:26:00.002-04:302010-06-27T19:22:22.571-04:30Common-Mode Control Techniques for Low Voltage Continuous-Time Analog Signal Processors<div class="post-header"></div><div class="post-body entry-content"><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_filelist.xml" rel="File-List"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_themedata.thmx" rel="themeData"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_colorschememapping.xml" rel="colorSchemeMapping"></link> <style>
<!-- /* Font Definitions */ @font-face {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4; mso-font-charset:0; mso-generic-font-family:roman; mso-font-pitch:variable; mso-font-signature:-1610611985 1107304683 0 0 159 0;} @font-face {font-family:Calibri; panose-1:2 15 5 2 2 2 4 3 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:-1610611985 1073750139 0 0 159 0;} @font-face {font-family:TimesNewRoman; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-alt:"MS Mincho"; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:0 134676480 16 0 131073 0;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {mso-style-unhide:no; mso-style-qformat:yes; mso-style-parent:""; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:0cm; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoPapDefault {mso-style-type:export-only; margin-bottom:10.0pt; line-height:115%;} @page Section1 {size:612.0pt 792.0pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} -->
</style><br />
<div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><b><span lang="EN-US"></span></b></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><b><span lang="EN-US"></span></b></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><b><span lang="EN-US"></span></b></div><br />
<div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">Abstract-Fully-Differential (FD) circuits are unavoidable under low voltage power supply conditions. To properly operate FD circuits the use of common-mode feedback is compulsory. The conceptual approach to implement the common-mode feedback circuits is introduced. Furthermore, the use of common-mode feedforward techniques to enhance the common-mode rejection ratio is introduced. It is demonstrated that the simultaneous application of common-mode feedback and common-mode feedforward yields optimal performance with only an additional small overhead cost. <br />
<br />
<b>I. INTRODUCTION</b> </span> <span style="font-size: small;"><br />
<br />
The rapid size reduction of CMOS technologies is limiting the maximum power supply voltage that integrated circuits (IC) can sustain, and this trend [1] will continue. In a digital IC, as devices dimensions shrink, more and more devices can be fabricated on the same die, the parasitic capacitances also tend to decrease, and current density increases. The combined effect is a reduction of the propagation delay, which allows higher throughput and clock rates for digital circuits. The performance of digital circuits improves with the size reduction of the technology. Unfortunately, from a general point of view, technology scaling has a negative impact on the performance of analog integrated circuits. Therefore, scaling degrades the intrinsic gain of the devices and, what is even more critical, the very limited voltage room available reduces the circuit dynamic range (DR) with respect to the DR counterparts for higher supply voltages. Therefore, in such low supply voltage (LV) conditions, analog circuits require larger input/output voltage signal swings, enhanced linearity, and larger rejection to undesired signals, to keep a similar performance with respect to the operation at higher supply voltages. Many analog design issues, which were unimportant only a decade ago, are now of vital importance and new circuit topologies and design strategies must be investigated for supply voltages in the order of one MOS transistor threshold voltage [2]. In this papers, the type and control of the common-mode (CM) component of (differential) signals in LV analog signal processors, is presented. Traditionally, common-mode feedback (CMFB) techniques have been applied for the control of the output CM component in (FD) circuits. However, most of the conventional techniques are not valid for very LV applications and hence, alternative solutions are needed. The merging of common-mode feedforward and common-mode feedback techniques to enhance circuit performance will be introduced. </span> <span style="font-size: small;"><br />
<br />
<b>II COMMON-MODE FEEDBACK PRINCIPLES </b></span> <span style="font-size: small;"><br />
<br />
One of the most useful building blocks in analog signal processors is the operational amplifier (Op Amp) or operational transconductance amplifier (OTA). For small size technologies the power supply is limited, but the output signal swing still needs to be large. One solution to increase the output signal is to use fully differential amplifiers. That is both differential input and differential output. Fig. 1 illustrates the conceptual architecture of the use of common-mode feedback. The basic idea is to first monitor the common-mode signal (that is the sum of the output signals) and then compare the common mode signal with a reference voltage, which usually is 0 volts. Thus a correction signal is generated and applied to the fully differential amplifier, such that eventually the correction signal becomes near to zero. The correction signal is the difference between the common-mode signal and the reference voltage. Fig. 2 illustrates an actual implementation of the conceptual architecture of Fig. 1. Fig. 2(a) and (b) illustrate the block and transistor level representation. The two stage differential amplifier has its two outputs connected to two simple differential amplifiers (M21-M24). The outputs of the simple amplifiers are added (in M25) and the corresponding output current is applied to the tail current (M5). The sensing of the output signals can be done in voltage as shown before, but it can be carried out in current. This principle is illustrated in Fig. 3. The amplifier is a transconductance amplifier. This transconductance amplifier consists of a differential pair and two current-mirrors. The common-mode level sensing circuit is applied to the sense amplifier where is compared with a reference current. The output of this CM sense amplifier is then injected to output bias current of the FD amplifier.</span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEinJgnpKDP8ZM837Ojo7V-Dgnme8l3_T1tt0U8rGhKzVoU8sWN7OCDbuZmHPtXR5aXslu0NdNvcHVkopkIg5p5ZJnJDcdfMT9Th3FuvCu5rIkQNGRTpAK_5yu0RpiGjUByLOVAOEVosP08/s1600/Dibujo1.JPG" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="291" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEinJgnpKDP8ZM837Ojo7V-Dgnme8l3_T1tt0U8rGhKzVoU8sWN7OCDbuZmHPtXR5aXslu0NdNvcHVkopkIg5p5ZJnJDcdfMT9Th3FuvCu5rIkQNGRTpAK_5yu0RpiGjUByLOVAOEVosP08/s400/Dibujo1.JPG" width="400" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><br />
<span style="font-size: small;">The use of common-mode feedback has as objective to: i) cancel the common-mode output signals; ii) fix the DC operating point at the output that maximizes the differential voltage gain. In addition the use of common-mode feedback should reduce the output noise. The actual implementation of the common-mode feedback is not trivial. Several design issues need to be taken into consideration to provide an implementation with the desired specifications and performance. Among them we need to minimize the loading effects of the amplifier when is connected to the sensing amplifier. Stability of the amplifier with feedback must be well defined. Another even more critical issue is the bandwidth of the loops associated with the differential-mode and the common-mode loops. These loop bandwidths should be of the same order to yield a good commonmode rejection ratio in the frequency range of interest. The DC gain of the CMFB loop must be large enough to keep an accurate control the CM component. If not, an asymmetrical swing occurs which entails a loss in the DR. The gain-bandwidth product of the CMFB loop (LGBWCM) should be at least equal to the gain-bandwidth product of the DM loop (LGBWDM) counterpart. We can consider common-mode feedback at the input and output port. Thus if LGBWCM,o < LGBWDM, the system does not perform as a fully-balanced systems in the range of frequencies comprised between LGBWCM,o and LGBWDM; while if LGBWCM,i < LGBWDM occurs, the amplifier does not operate properly since the input CM voltage can be out of the amplifier input CMR in the frequency band comprised between LGBWCM,i and LGBWDM. The CMFB loop must only act over CM voltage signal, while does not affect to any DM voltage signal. If this not occurs, harmonic distortion by the CMFB loop is induced in the signal.</span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgrKqRh6uiYgTYOwbXQhQ3h79C77w3aMhF2ePWSK-W_kMnVDl9h07L8uh9KJvaTwAYKcK4kYAnx6tN2OiBkynBRG8XfciWzLLFDhQv5pNCZD6vIGGQcizgUzEHgvBLZjrEmSPn7r2N2_J0/s1600/Dibujo2.JPG" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="290" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgrKqRh6uiYgTYOwbXQhQ3h79C77w3aMhF2ePWSK-W_kMnVDl9h07L8uh9KJvaTwAYKcK4kYAnx6tN2OiBkynBRG8XfciWzLLFDhQv5pNCZD6vIGGQcizgUzEHgvBLZjrEmSPn7r2N2_J0/s400/Dibujo2.JPG" width="400" /></a></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgcY56Cfhqq2P8MlDZgT43mftZgyPOxFFe9dyrbcS4U91IScM8ROXQvugnLjZG1QhnS2bbrW5_5ascYouLJZ0f_LmoVdGQ-ESsyifST55h1HesqP8jnVrpkCcjIYhtlYJqE8F0mDQ-XXZc/s1600/Dibujo3.JPG" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="242" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgcY56Cfhqq2P8MlDZgT43mftZgyPOxFFe9dyrbcS4U91IScM8ROXQvugnLjZG1QhnS2bbrW5_5ascYouLJZ0f_LmoVdGQ-ESsyifST55h1HesqP8jnVrpkCcjIYhtlYJqE8F0mDQ-XXZc/s400/Dibujo3.JPG" width="400" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"></span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><br />
<span style="font-size: small;"><b>III COMMON-MODE-FEEDFORWARD TECHNIQUES </b></span> <span style="font-size: small;"><br />
<br />
The use of common-mode Feedforward (CMFF) is very desirable; however note that using only CMFF is not sufficient. CMFF can help to reduce drastically the output common-mode signals, but it cannot help to stabilize the DC output operating bias. The conceptual representation of the CMFF is shown in Fig. 4(a). In the case of multiple cascade amplifiers we can make clever use of CMFF as shown in Fig. 4(b). Note that the common-mode feedforward detector is part of the amplifier; also note that the detection is not done in the amplifier itself but in the next one in the cascade stages. Then a simple feedback is implemented from say amplifier 2 to amplifier 1. One potential transistor level implementation [10] is shown in Fig. 5. Observe in this figure the symmetry and balance of the topology that yields optimal performance as shown later.</span><br />
<span style="font-size: small;"> <b> </b></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjCiVQdoqPrJAVsJa37FgDccElwiHURaP751jZG-G5EcjzEA5vGrnEEUUhNGQOpgyE8pC1KohK6GAaK4E_ujfswUCVHov7oI7oVSRhcwDl4XVGZ4Ok-1UtcFHI8RftY8ZN6jw6V64BvLQs/s1600/Dibujo4.JPG" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="195" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjCiVQdoqPrJAVsJa37FgDccElwiHURaP751jZG-G5EcjzEA5vGrnEEUUhNGQOpgyE8pC1KohK6GAaK4E_ujfswUCVHov7oI7oVSRhcwDl4XVGZ4Ok-1UtcFHI8RftY8ZN6jw6V64BvLQs/s400/Dibujo4.JPG" width="400" /></a></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjjyXn8z67onQ1ay7ISp7Mfsy54IXJwfslZ2rHVpojECzCm636_jBU1SuB08H8a1-t350ExfH1kyI1flNBhMjddQpCC9RFCwCakH5lS350cxLzD8BSa8pC4dMI-u8Bb0rTmb0eVM63Y2ho/s1600/Dibujo5.JPG" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="211" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjjyXn8z67onQ1ay7ISp7Mfsy54IXJwfslZ2rHVpojECzCm636_jBU1SuB08H8a1-t350ExfH1kyI1flNBhMjddQpCC9RFCwCakH5lS350cxLzD8BSa8pC4dMI-u8Bb0rTmb0eVM63Y2ho/s400/Dibujo5.JPG" width="400" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"></span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><br />
<span style="font-size: small;"><b>IV AN EXAMPLE OF CMFB AND CMFF TECHNIQUES </b></span> <span style="font-size: small;"><b><br />
</b><br />
In this example we show the effect of the CMRR for three different cases. That is a) CMFF only, b) CMFB only, c) CMFB + CMFF. Fig. 6 shows how the combination of the two common-mode techniques yields around 80 dB. Furthermore, the linearity of the amplifier is improved by using both common-mode techniques. Fig. 7 shows that we can obtain up 1.2 peak to peak differential input with less than 1% THD for a 3.3V power supply.</span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg80exzE6XtO0Yc2MMtClIHBd_PbfJfErYChZL0gtrck2qLlJO-mkRicc6i9aoOTWn3em2t2QX4jBk_GekkHfwF_3sNuUMKNVxQbQIB4cBjHL4LinuGu2iE73xnjT3ySWUkv2YKSIdguvk/s1600/Dibujo6.JPG" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="400" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg80exzE6XtO0Yc2MMtClIHBd_PbfJfErYChZL0gtrck2qLlJO-mkRicc6i9aoOTWn3em2t2QX4jBk_GekkHfwF_3sNuUMKNVxQbQIB4cBjHL4LinuGu2iE73xnjT3ySWUkv2YKSIdguvk/s400/Dibujo6.JPG" width="400" /></a></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgUkE_spfTXAA5rSsiRtLReEFL_bNcOjIsSY1L0N5pfmZwE5Ltc7bbCxDVFpk4j9D3cOcMHiTgQlMTQHvrizc6MIoYgxpb8VlK71056yicPNoQTgIkipBlhqZgfHWyG0-4bLYBXIa4QTNI/s1600/Dibujo7.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="305" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgUkE_spfTXAA5rSsiRtLReEFL_bNcOjIsSY1L0N5pfmZwE5Ltc7bbCxDVFpk4j9D3cOcMHiTgQlMTQHvrizc6MIoYgxpb8VlK71056yicPNoQTgIkipBlhqZgfHWyG0-4bLYBXIa4QTNI/s400/Dibujo7.bmp" width="400" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"></span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><br />
<span style="font-size: small;"><b>V CONCLUSIONS </b></span> <span style="font-size: small;"><br />
<br />
A brief introduction to common-mode feedback concepts has been introduced. The key issue in this paper is the strategic use of jointly of the common-mode feedforward and common-mode feedback yielding optimal results for common-mode rejection ratio as well as an improved linearity. More details about LV amplifiers common-mode feedback techniques are available elsewhere.</span><br />
<br />
</div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">Hernández Caballero Indiana<br />
Asignatura: CAF<br />
Fuente:<a href="http://www.emo.org.tr/ekler/bc10d8a74dbafbf_ek.pdf">http://www.emo.org.tr/ekler/bc10d8a74dbafbf_ek.pdf</a> </span></div></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-92055918594498871022010-06-25T20:17:00.002-04:302010-06-27T19:21:18.117-04:30It's not just 50 ohms: Some termination tips for differential and single-ended amplifiers<h3 class="post-title entry-title"><a href="http://indianamaithe.blogspot.com/2010/06/its-not-just-50-ohms-some-termination.html"></a> </h3><div class="post-header"></div><div class="post-body entry-content"><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_filelist.xml" rel="File-List"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_themedata.thmx" rel="themeData"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_colorschememapping.xml" rel="colorSchemeMapping"></link> <style>
<!-- /* Font Definitions */ @font-face {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4; mso-font-charset:0; mso-generic-font-family:roman; mso-font-pitch:variable; mso-font-signature:-1610611985 1107304683 0 0 159 0;} @font-face {font-family:Calibri; panose-1:2 15 5 2 2 2 4 3 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:-1610611985 1073750139 0 0 159 0;} @font-face {font-family:TimesNewRoman; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-alt:"MS Mincho"; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:0 134676480 16 0 131073 0;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {mso-style-unhide:no; mso-style-qformat:yes; mso-style-parent:""; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:0cm; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoPapDefault {mso-style-type:export-only; margin-bottom:10.0pt; line-height:115%;} @page Section1 {size:612.0pt 792.0pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} -->
</style> <br />
<div class="MsoNormal" style="text-align: justify;"><span lang="EN-US" style="font-family: TimesNewRoman, serif; font-size: 10pt; line-height: 115%;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Termination - the term brings to mind different values of resistance to different specialties in electronics. RF designers think about 50 ohm, video designers 75 ohm, audio and telecommunication designers 600 ohm - there are many possibilities. All of these termination resistor values have a common purpose - they match impedances in the circuit and therefore attenuate reflections that would otherwise cause problems in the system.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">This article will focus on 50-ohm terminations - but this has more to do with the test equipment available in the author's lab than a preference for RF applications. The techniques established here are applicable to any value of termination resistor, because the electrical laws governing them are universally applicable to other resistance values.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">For every input termination resistor, there needs to be a companion series-matching resistor in the source. A laboratory signal source will be assumed. Laboratory sources can be thought of as an ideal voltage source (zero ohm output impedance) in series with a 50 ohm resistor. This resistor is shown as Rs in the schematics below. Laboratory sources assume a 50 ohm termination in the circuit that is driven, and take it into account when generating their display.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">For example, a laboratory source is set to 1 Vpp. An ideal source (internal to the instrument and inaccessible to the user) produces a 2 Vpp output. This 2 Vpp output is applied to the internal 50 ohm series-matching resistor. If the source is monitored with a high impedance-measuring instrument -V an oscilloscope with a 1 M-ohm input, for example, it would produce very nearly 2 Vpp - even though the output indicator on the instrument indicates 1 Vpp. When the same source is monitored with an instrument that has a 50 ohm input, the output would be 1 Vpp because Rs and Rt produce a 2:1 voltage divider at the circuit input.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">It is very important to realize that the only voltage available to the instrument user is the voltage at its output connector (after the 50 ohm source resistor). Instrument accuracy is only as good as its internal accuracy, as modified by the input termination resistor of the circuit.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">It is worth a brief mention that 50 ohm is not a standard one percent resistor value. The closest standard value is 49.9 ohm, and this value has been used in the examples below.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Four cases will be covered in this article: Inverting Stage attenuators Non inverting stage attenuators Single-ended to fully differential stages Differential to fully differential stages</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;"><b>Single-Ended Op Amps</b></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Single-ended op amps are a mature technology - therefore some of what is presented here may be a review. The inverting case, however, is subtle and needs explanation. Inverting Stage Attenuators</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;"></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Consider the circuit of represented in Figure 1. It assumes a laboratory source as described above. Most designers assume that the 49.9 ohm termination resistor, combined with resistors Rg and Rf will guarantee a gain of 1 - but wait! The real story is a little more complicated.</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgtfkwapFDMU0HuvZpDV8RR_veeeIoYCF-aYRIw_A0Lk1NyO5Bvfv_3D6x-Vv0vPD89tQv_gq0tLqFsiHNpySYqocS_wq-ODsKZh_5BilB7xnm2m2zq6Q2mDIRz0RSLWJNxe3oFw78ED1o/s1600/fig1.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgtfkwapFDMU0HuvZpDV8RR_veeeIoYCF-aYRIw_A0Lk1NyO5Bvfv_3D6x-Vv0vPD89tQv_gq0tLqFsiHNpySYqocS_wq-ODsKZh_5BilB7xnm2m2zq6Q2mDIRz0RSLWJNxe3oFw78ED1o/s320/fig1.jpg" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: center;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;"> Figure 1. Inverting Gain Stage</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Assume that the signal source is a laboratory source set to 1 VPP. Both Rg and Rt affect the level of voltage applied to the circuit. The function generator indicates a level of plus-minus 0.5 V (1 VPP) - while only plus-minus 0.484 V (0.968 VPP) is applied to the board. The user might wonder, "what happened - where did the rest of the voltage (plus-minus 0.016 V) go"?</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">There are two ways of looking at this problem:</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">From the function generator side. The function generator contains a 50 source resistor. The EVM contains a 49.9 ohm termination resistor, and therefore the output of the function generator will see (approximately) a 2:1 voltage divider. The function generator anticipates this, and scales its output accordingly.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">In the inverting configuration, however, the inverting input presents a ground potential to the gain resistor Rg. This is because the ideal op amp model forces both inputs to the same voltage potential. The non-inverting input is connected to ground, and therefore the inverting input will also be at ground. The resulting impedance resistance for the stage will therefore be equal to the termination resistor in parallel to Rg, in this case 750 ohm. Therefore, the instrument output is actually:</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhoj2IBm8MQZloCxpDZGaD1Asss06z8LbjcW9RGWYLzDamH2qAWJ5fmTiy_lhsB5p_AaM80DN-ve-XpR7sdty9PYmqQRVsjta0kyniotSu47N1exVLBScVk-mouUOxE6gZeVT7j2J9Sr_U/s1600/eq1.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhoj2IBm8MQZloCxpDZGaD1Asss06z8LbjcW9RGWYLzDamH2qAWJ5fmTiy_lhsB5p_AaM80DN-ve-XpR7sdty9PYmqQRVsjta0kyniotSu47N1exVLBScVk-mouUOxE6gZeVT7j2J9Sr_U/s320/eq1.jpg" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">This can also be viewed as the Thevenin equivalent voltage looking into the source at Rt.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">From the circuit side. The Thevenin equivalent resistance of the circuit plus the source - looking towards the source from the inverting input of the op amp is:</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhhF6knzXkAIfUhytq4V8C1qk_24DDz0JPWtz4SVBSwnBFh-DMfpP-1cMmaKYVAbvKkqClQ_iaMKGHv1oFbJ6ua1fZruuljnenIxFalOyu4rGcj2R7fshQg3ei240-f3Tf9WE0d9fSiIdA/s1600/eq2.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhhF6knzXkAIfUhytq4V8C1qk_24DDz0JPWtz4SVBSwnBFh-DMfpP-1cMmaKYVAbvKkqClQ_iaMKGHv1oFbJ6ua1fZruuljnenIxFalOyu4rGcj2R7fshQg3ei240-f3Tf9WE0d9fSiIdA/s320/eq2.jpg" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Therefore, the inverting gain on a 0.5 Vpeak ideal voltage source (assumed to be embedded in the function generator) is:</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj2dUVSAMhHMEpAoLXEykb0nvytqeRgAqDAREtuIidftB1lkyn6VET9vn7FYUhTdXC3WAOpQPNtXvCvgVOughadaLRdZ2gil-rb4Tcz599tMc_KI4WPJyW5cmkFO4xlH9c8UiIEC6-D78k/s1600/eq3.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj2dUVSAMhHMEpAoLXEykb0nvytqeRgAqDAREtuIidftB1lkyn6VET9vn7FYUhTdXC3WAOpQPNtXvCvgVOughadaLRdZ2gil-rb4Tcz599tMc_KI4WPJyW5cmkFO4xlH9c8UiIEC6-D78k/s320/eq3.jpg" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">The two results are equivalent.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;"><b>Non-Inverting Stage Operation</b></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">The circuit of Figure 2 contains a 50 ohm terminated input (Rt), and gain setting resistors. Because Rt does not appear in parallel with Rg as in the inverting case, the gain calculation is much simpler - and the termination resistor does not affect the gain expression that the designer is probably familiar with: </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjq-SI2ccO4Ww3jue2z_2T4U129i2vqC1MnkP5iHwFst7gcYs-yEL4cFqfAu_BNGRhezxQ_dc-4Ejacuof1YafQyFq-ZQTHZ32C6Pc4zeO41XwQRbWYa-ujBm07mZfn0RfULRg9IdAOaMo/s1600/eq4.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjq-SI2ccO4Ww3jue2z_2T4U129i2vqC1MnkP5iHwFst7gcYs-yEL4cFqfAu_BNGRhezxQ_dc-4Ejacuof1YafQyFq-ZQTHZ32C6Pc4zeO41XwQRbWYa-ujBm07mZfn0RfULRg9IdAOaMo/s320/eq4.jpg" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;"><br />
</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjDypxsaBBy9N_6LA_iKpSSXsUiE73wf1OIXnO_Gdlv4Z4RcaKPUmOAYEr8iQnDtLJTCL8lvSuTuciM-ES7kbwfDBolzgB84PDOOn5fIu0IIwkikSxMSA_kJpXESks869fDZD8G4R9CYWs/s1600/fig2.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjDypxsaBBy9N_6LA_iKpSSXsUiE73wf1OIXnO_Gdlv4Z4RcaKPUmOAYEr8iQnDtLJTCL8lvSuTuciM-ES7kbwfDBolzgB84PDOOn5fIu0IIwkikSxMSA_kJpXESks869fDZD8G4R9CYWs/s320/fig2.jpg" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: center;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Figure 2. Non-Inverting Gain Stage Figure</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;"><b>Fully Differential Op Amps</b></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Fully differential op amps present some special challenges for terminated operation, because they should have two balanced feedback loops for symmetrical operation. Termination presents some special problems for this requirement.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Two cases will be discussed. One is single ended signal input, the other fully differential signal input.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;"><b>Single-Ended to Fully Differential Conversion</b></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Termination is applied to one of the two inputs - the other input is grounded as shown in Figure 3. This automatically creates an imbalance in the two feedback loops. Some of the reasons are described in the section above - all of that analysis applies to the bottom feedback path. </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEifl7qkhuZgcPk9hAkF7LVcuTcBE7PoDpre4Fpg-YWKGMgmrBHgu1kS3QrBA9EzrG7x07F1dDqOykldWOIYwUb1fj-uv4cqSa7x-DUHqlwcpEf4rY7DXYgnkaPdhyphenhyphen2Jjy9PAnoXcW3e2j8/s1600/fig3.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEifl7qkhuZgcPk9hAkF7LVcuTcBE7PoDpre4Fpg-YWKGMgmrBHgu1kS3QrBA9EzrG7x07F1dDqOykldWOIYwUb1fj-uv4cqSa7x-DUHqlwcpEf4rY7DXYgnkaPdhyphenhyphen2Jjy9PAnoXcW3e2j8/s320/fig3.jpg" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: center;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Figure 3. Single-Ended to Fully Differential</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">The overall effect, of course, is to place 25 more ohms on the bottom feedback path than on the top (Rs || Rt + R3). This means that the gain on the bottom feedback path is less than that of the top. So, 25 ohms must also be added to R1. But this changes the gain of the entire circuit to less than 1, so both R1 and R3 must both be decreased to boost the gain. This could go one and on - the design is an interactive process. To simplify this task for designers, Texas Instruments provides an on-line calculator on its web site. This tool can be accessed either through the Analog and Mixed-Signal Knowledgebase, or through the Engineering Design Utilities section on the Analog and Mixed Signal portion of the TI web site. </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiV_ZLOGNlyCxG4Gzw1p6ETrh1r-e9_pai9eyh4ljMbzkgULj-7Z0eALe93DL-5XktsiP2y-s-UecyIDDXZatKlIVpZ_i8PrPwdlzRYAW5f2GXN-7MJnQPZ0hxGhOglnnu7pRAyPSuPtgE/s1600/fig4.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="281" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiV_ZLOGNlyCxG4Gzw1p6ETrh1r-e9_pai9eyh4ljMbzkgULj-7Z0eALe93DL-5XktsiP2y-s-UecyIDDXZatKlIVpZ_i8PrPwdlzRYAW5f2GXN-7MJnQPZ0hxGhOglnnu7pRAyPSuPtgE/s400/fig4.jpg" width="400" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: center;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Figure 4 shows a screen shot of the fully differential amplifier component calculator.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">The fully differential component calculator has six panes. Data entry is primarily made in the upper left pane, although the bottom middle pane contains some secondary entry fields.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">The top middle pane contains the schematic for a terminated single-ended to fully differential conversion. Design equations are shown in the upper right hand pane. The equations for RR3,R4 and Rt are interrelated through the ''A'' parameter. The tool will make a preliminary calculation to get close to the correct values, and then it will refine the calculation and ''goal seek'' to the final value. The execution time depends on the step size used in the goal seeking calculation, and therefore selecting ''E96'' resistor values will execute much faster than ''Exact'' values. The designer should be patient, because execution times of several seconds or longer are possible, especially if gain is changed radically when ''Exact Values'' is selected. The designer selects the desired gain and the impedance of the signal source (default value of 50 ohms). The designer then has the option of selecting a seed value for either R3 or R4 (but not both). If the designer attempts to select both, only the last value entered will be used for calculation.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Almost without exception, the designer should initially try to select the value of R4, because it is often specified on the data sheet. The designer should experiment with R3 only if the recommended value of R4 does not yield an acceptable design (the tool has internal limits set to resistor values that make sense for real designs).</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">When the designer selects ''Calculate Values,'' the tool will calculate resistor values in the bottom left pane and circuit simulation results in the bottom right pane. If the designer wishes, the power and input voltages can be changed in the bottom middle pane, and these will affect the simulation results in the bottom right.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Note that this tool provides dc operating point only - it does not give ac simulation. Nevertheless, it will save the designer a lot of grief trying to do it the ''brute force'' method.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">The implementation of Figure 5 is completely equivalent to that of Figure 3, it does not matter which input is used for the signal. </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglFScSKO6-dO0Oa6xVr-HLkLN_vkqkUTtQwdPeR5BrnnafeqXIdaI3bIAKfMsOwr69eW-seUaRyqXBafuvpw4OO5eswM6g0Edrim0iUo79oDm9DmxsNeIi9s-lp34npJAIkClIMQK-aHA/s1600/fig5.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEglFScSKO6-dO0Oa6xVr-HLkLN_vkqkUTtQwdPeR5BrnnafeqXIdaI3bIAKfMsOwr69eW-seUaRyqXBafuvpw4OO5eswM6g0Edrim0iUo79oDm9DmxsNeIi9s-lp34npJAIkClIMQK-aHA/s320/fig5.jpg" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: center;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Figure 5. Alternative Single-Ended to Fully Differential Conversion</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;"><b>Fully-Differential In/Fully-Differential Out</b></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Consider the circuit of Figure 6. In this configuration, input termination (resistor R1), is used to terminate a fully differential input.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Fully differential gain for the un-terminated case is determined by the relationship:</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgWCban42X7TGNGiz0t2OvzNd-WYjFzpBdMMV6erHKV43beSFnz6JSt5JPiLo3D2ExBTUEXxHYOkk1asZfa2mHAwZqpfqYJL70_rXZWeLKAxd1pwaj3a4UvQJIZMpRWtqt-GakC5VPendc/s1600/eq5.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEgWCban42X7TGNGiz0t2OvzNd-WYjFzpBdMMV6erHKV43beSFnz6JSt5JPiLo3D2ExBTUEXxHYOkk1asZfa2mHAwZqpfqYJL70_rXZWeLKAxd1pwaj3a4UvQJIZMpRWtqt-GakC5VPendc/s320/eq5.jpg" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;"> Where Rf is R3 in the top feedback loop and R6 in the bottom, and Rg is R2 on top and R5 on the bottom.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">The designer should recognize the gain expression as being very close to the expression for the single-ended inverting stage (but without the negative sign). There is no negative sign because it is meaningless when both polarities of output are simultaneously available. </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhDKIw4hxcSpY6Au3JJ4ZdOynJvppLlzUV_R7G5jn6VjYa8VeHeuYV9MWzDBZRobhell7wPwThPKw3Q1FU1wjLsi1PbNMeDWFdPtPzj8kPYORxWw7THtRk8Id6PWKuXbQ-cpQFf4gIRo8c/s1600/fig6.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhDKIw4hxcSpY6Au3JJ4ZdOynJvppLlzUV_R7G5jn6VjYa8VeHeuYV9MWzDBZRobhell7wPwThPKw3Q1FU1wjLsi1PbNMeDWFdPtPzj8kPYORxWw7THtRk8Id6PWKuXbQ-cpQFf4gIRo8c/s320/fig6.jpg" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: center;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Figure 6. Fully Differential Operation</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">When a termination resistor is used, it affects the gain in a manner similar to the single-ended cases. In this case, however, the effect is not as intuitive.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Figure 7 shows the input of a differential stage as an ideal voltage source, with its characteristic 50 ohm source impedance split in two parts, between a "phantom ground". The termination resistor is also shown in two parts between the same phantom ground. The end result is the two 25 ohm resistors above the phantom ground appearing as a single 12.5 ohm resistor (the parallel combination). This 12.5 ohm resistance appears in series with the top Rg, changing the gain. Similarly, the two 25 ohm resistors below the phantom ground add to the bottom Rg, changing the gain and balancing the top gain.</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhuuLWHlRw8OVlgvAubcazqC6BSWhajKdpIyLa8eu1F1lLKAlUHzEHxE7Go9OZ5-W9Z9z1pfNWMno5ZO5Gkrwns5FTOXTZe0pUzKVNX0AVjE4BRNNFsGw5zDsADpic6_qM7xPKXgluNbGg/s1600/fig7.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhuuLWHlRw8OVlgvAubcazqC6BSWhajKdpIyLa8eu1F1lLKAlUHzEHxE7Go9OZ5-W9Z9z1pfNWMno5ZO5Gkrwns5FTOXTZe0pUzKVNX0AVjE4BRNNFsGw5zDsADpic6_qM7xPKXgluNbGg/s320/fig7.jpg" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: center;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Figure 7. Fully Differential Operation</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">The gain of the fully differential stage, therefore, is:</span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhiBPH7KJbKfdGwfA_Ni6fBFpBfoDCGCkCNs0q7GcM7jQ14M9dxyMAvEo0b-1nd5aD0mJPx_GnfLbYhyphenhyphend5p-WDlv3KPFiCZrbLpHL4ElqBwz8lvjjqIgHsJnNeb2yCiFJrvB8QHpNl2B8Q/s1600/eq6.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhiBPH7KJbKfdGwfA_Ni6fBFpBfoDCGCkCNs0q7GcM7jQ14M9dxyMAvEo0b-1nd5aD0mJPx_GnfLbYhyphenhyphend5p-WDlv3KPFiCZrbLpHL4ElqBwz8lvjjqIgHsJnNeb2yCiFJrvB8QHpNl2B8Q/s320/eq6.jpg" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;"></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;"></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">For the circuit of Figure 6, the differential gain is: </span></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi4_IoeRmiPq2y-RGBEOhBwhJko6SH1D373nJCkfPzvx3onjlWX_hjW45GHOcU4Xn-DX_UYcXhpiVbw4dH2R66ENr46-Q_EWfIjn3HVVnTwN9fcYbjxVwWwGH0F4LR1mrZUHxghjhHedbA/s1600/eq7.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="60" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEi4_IoeRmiPq2y-RGBEOhBwhJko6SH1D373nJCkfPzvx3onjlWX_hjW45GHOcU4Xn-DX_UYcXhpiVbw4dH2R66ENr46-Q_EWfIjn3HVVnTwN9fcYbjxVwWwGH0F4LR1mrZUHxghjhHedbA/s400/eq7.jpg" width="400" /></a></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">Changing the gain is much more straightforward than in the previous case, because equal changes made to the top and bottom feedback loop simultaneously are inherently symmetrical.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;"><b>Output Series Resistor Matching</b></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">The circuits shown above can also be considered to be voltage sources. The output impedance of most op amp circuits (operated in a closed loop) is low enough that it can be considered to be zero. Therefore, it is a good approximation to consider closed loop op amp to be an ideal voltage source.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">The reader is reminded that in the discussion above, an ideal voltage source is assumed to be at the heart of a laboratory voltage source. Therefore, by extrapolation, the reader hopefully sees how to cascade terminated stages - by adding 50 ohms in series with the op amp output to create a 50 ohm "source" for the subsequent stage.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">This is often the case in RF design, where each stage has 50 ohm input and output. If the circuits above drive a 50 ohm load, they need a 50 ohm resistor in series with the op amp output. This will, of course, create a 2:1 voltage divider (-6 dB) with the termination resistor in the subsequent stage. This has to be taken into account in the design of overall system gain. It takes 6 dB of stage gain to compensate for a 2:1 voltage divider. The -20 dB per decade slope of the open loop response of a typical voltage feedback op amp, combined with 6 dB of gain forces a designer to choose a part with approximately four times the bandwidth that would be required for a unity gain stage.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><span lang="EN-US" style="line-height: 115%;">The proper application of termination is a powerful way of suppressing reflections in high-speed circuits. It comes with a price; however, it introduces voltage dividers that attenuate the signal. Stage gain has to be increased to compensate - and that often times dictates a much higher bandwidth part to accommodate the additional gain required.</span></span></div><div class="MsoNormal" style="text-align: justify;"><span lang="EN-US" style="font-family: TimesNewRoman, serif; font-size: 10pt; line-height: 115%;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Termination can introduce subtle gain errors into a circuit if it effects are not properly taken into account. The rules governing termination are simple - Ohm's law, the voltage divider law, and the superposition principle - therefore it is not asking a great deal from analog designers to do the calculations. The only exception is the case of termination a single-ended to fully differential conversion, and Texas Instruments has provided a utility to simplify the task.</span></span></span></div><div class="MsoNormal" style="text-align: justify;"></div><div class="MsoNormal" style="text-align: justify;"><span lang="EN-US" style="font-family: TimesNewRoman, serif; font-size: 10pt; line-height: 115%;"><span style="font-size: small;"><span style="font-family: Verdana, sans-serif;">Hernández Caballero Indiana<br />
Asignatura: CAF<br />
Fuente:<a href="http://www.planetanalog.com/story/OEG20020724S0082">http://www.planetanalog.com/story/OEG20020724S0082</a> </span></span></span></div><div class="MsoNormal" style="text-align: justify;"><br />
</div></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-41144919067779952432010-06-25T20:15:00.002-04:302010-06-27T19:18:41.147-04:30Texas Instruments introduces a differential amplifier family<h3 class="post-title entry-title"><a href="http://indianamaithe.blogspot.com/2010/06/texas-instruments-introduces.html"></a> </h3><div class="post-header"></div><div class="post-body entry-content"><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_filelist.xml" rel="File-List"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_editdata.mso" rel="Edit-Time-Data"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_themedata.thmx" rel="themeData"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_colorschememapping.xml" rel="colorSchemeMapping"></link> <style>
<!-- /* Font Definitions */ @font-face {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4; mso-font-charset:0; mso-generic-font-family:roman; mso-font-pitch:variable; mso-font-signature:-1610611985 1107304683 0 0 159 0;} @font-face {font-family:Calibri; panose-1:2 15 5 2 2 2 4 3 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:-1610611985 1073750139 0 0 159 0;} @font-face {font-family:TimesNewRoman; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-alt:"MS Mincho"; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:0 134676480 16 0 131073 0;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {mso-style-unhide:no; mso-style-qformat:yes; mso-style-parent:""; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:0cm; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoPapDefault {mso-style-type:export-only; margin-bottom:10.0pt; line-height:115%;} @page Section1 {size:612.0pt 792.0pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} -->
</style> <br />
<div class="separator" style="clear: both; text-align: center;"><br />
</div><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjZ6H-uIfyU1pbP7Enpj-EO7ERwmEgJWoYwQADoGJytLNM3utgiUC8l0rJtdWgTP3BeRrklkagGtk_dO2mPLEzAIKnDZ2DvXt4cJ-2o6zc4au3pAn_CXU3W3f6RgN5oX73iI5kzFmfBEow/s1600/image.php.jpg" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="288" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjZ6H-uIfyU1pbP7Enpj-EO7ERwmEgJWoYwQADoGJytLNM3utgiUC8l0rJtdWgTP3BeRrklkagGtk_dO2mPLEzAIKnDZ2DvXt4cJ-2o6zc4au3pAn_CXU3W3f6RgN5oX73iI5kzFmfBEow/s320/image.php.jpg" width="320" /></a><br />
<div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span lang="EN-US" style="font-family: TimesNewRoman, serif; font-size: 10pt;"><br />
</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">Texas Instruments has introduced a fully differential amplifier family that drives high accuracy data conversion across single and multi-channel SAR (successive approximation register) and delta-sigma ADCs (analogue-to-digital converters) in a wide range of applications including industrial, medical and audio. The THS4521, THS4522 and THS4524 provide good performance to power ratio, making the devices suitable for applications requiring high resolution and precision with high dynamic range, such as pressure and flow meters, seismic equipment and electrocardiogram machines, as well as battery-operated devices and other applications with sensitive power budgets. This product family provides an alternative that reduces the number of amplifiers to save board space and alleviates amplifier and circuit matching concerns while minimising power consumption.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;">The devices consume low quiescent current of 1.14mA per channel and less power down current of 20uA. The family increases the bandwidth by more than 30%, providing 145MHz and 490V/μs slew rate to buffer and amplify signals without increasing the system power consumption. It improves dynamic range/sensitivity by 44% with an input voltage noise of 4.6nV/rtHz to minimise distortion. The output common mode control allows easy DC coupling, while negative rail input and rail-to-rail output capability simplifies design and shortens development time. The device offers power supply flexibility by accepting single supply of +3 to +5V or dual supply of ±1.5 to ±2.5V. The amplifier reduces board space with single, dual and quad configuration options.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span lang="EN-US" style="font-family: TimesNewRoman, serif; font-size: 10pt;"><span style="font-family: Verdana, sans-serif; font-size: small;">The amplifier devices enable customers to drive differential ADCs, including the company's ADS8317 16bit, 250ksamples/s SAR converter and ADS1278 24bit, 128ksamples/s delta-sigma converter and achieve specified data sheet performance levels. For instance, using the THS4521 to buffer the ADS1278, at 10kHz input achieves 102dB SNR (signal-to-noise ratio) and 110dBc SFDR (spurious free dynamic range) with low quiescent current, which reduces system power consumption.</span></span></div><div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div style="text-align: justify;"><span style="font-family: Verdana, sans-serif; font-size: small;">Hernández Caballero Indiana</span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Asignatura: CAF</span><br />
<span style="font-family: Verdana, sans-serif; font-size: small;">Fuente:<a href="http://www.epn-online.com/page/new112261/texas-instruments-introduces-a-differential-amplifier-family.html">http://www.epn-online.com/page/new112261/texas-instruments-introduces-a-differential-amplifier-family.html</a></span></div></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-47263037452628806752010-06-25T20:10:00.002-04:302010-06-27T19:18:10.042-04:30Fully differential amplifier<div class="post-header"></div><div class="post-body entry-content"><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_filelist.xml" rel="File-List"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_themedata.thmx" rel="themeData"></link><link href="file:///C:%5CDOCUME%7E1%5CINDIANA%5CCONFIG%7E1%5CTemp%5Cmsohtmlclip1%5C01%5Cclip_colorschememapping.xml" rel="colorSchemeMapping"></link> <style>
<!-- /* Font Definitions */ @font-face {font-family:"Cambria Math"; panose-1:2 4 5 3 5 4 6 3 2 4; mso-font-charset:0; mso-generic-font-family:roman; mso-font-pitch:variable; mso-font-signature:-1610611985 1107304683 0 0 159 0;} @font-face {font-family:Calibri; panose-1:2 15 5 2 2 2 4 3 2 4; mso-font-charset:0; mso-generic-font-family:swiss; mso-font-pitch:variable; mso-font-signature:-1610611985 1073750139 0 0 159 0;} @font-face {font-family:TimesNewRoman; panose-1:0 0 0 0 0 0 0 0 0 0; mso-font-charset:0; mso-generic-font-family:roman; mso-font-format:other; mso-font-pitch:auto; mso-font-signature:3 134676480 16 0 131073 0;} /* Style Definitions */ p.MsoNormal, li.MsoNormal, div.MsoNormal {mso-style-unhide:no; mso-style-qformat:yes; mso-style-parent:""; margin-top:0cm; margin-right:0cm; margin-bottom:10.0pt; margin-left:0cm; line-height:115%; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoChpDefault {mso-style-type:export-only; mso-default-props:yes; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:Calibri; mso-fareast-theme-font:minor-latin; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi; mso-fareast-language:EN-US;} .MsoPapDefault {mso-style-type:export-only; margin-bottom:10.0pt; line-height:115%;} @page Section1 {size:612.0pt 792.0pt; margin:70.85pt 3.0cm 70.85pt 3.0cm; mso-header-margin:36.0pt; mso-footer-margin:36.0pt; mso-paper-source:0;} div.Section1 {page:Section1;} -->
</style> <br />
<div class="MsoNormal" style="line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span lang="EN-US" style="font-family: TimesNewRoman, serif; font-size: 10pt;"></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US">A fully differential amplifier , usually referred to as an 'FDA ' for brevity, is a DC- coupled high-gain electronic voltage amplifier with differential inputs and differential outputs. In its ordinary usage, the output of the FDA is controlled by two feedback paths which, because of the amplifier's high gain, almost completely determines the output voltage for any given input.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b>The ideal FDA</b></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US">For any input voltages the ideal FDA has infinite open-loop gain, infinite bandwidth, infinite input impedances resulting in zero input currents, infinite slew rate, zero output impedance and zero noise.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US">A Real FDA can only approximate this ideal, and the actual parameters are subject to drift over time and with changes in temperature, input conditions, etc. Modern integrated FET or MOSFET FDAs approximate more closely to these ideals than bipolar ICs where large signals must be handled at room temperature over a limited bandwidth; input impedance, in particular, is much higher, although the bipolar FDA usually exhibit superior (i.e., lower) input offset drift and noise characteristics.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US">Where the limitations of real devices can be ignored, an FDA can be viewed as a Black Box with gain; circuit function and parameters are determined by feedback, usually negative. An FDA as implemented in practice is moderately complex integrated circuit</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><b><span lang="EN-US">Limitations of real FDAs</span></b></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b>DC imperfections</b></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Finite gain —</b> the effect is most pronounced when the overall design attempts to achieve gain close to the inherent gain of the FDA.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Finite input resistance —</b> this puts an upper bound on the resistances in the feedback circuit.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Nonzero output resistance —</b> important for low resistance loads. Except for very small voltage output, power considerations usually come into play first. (Output impedance is inversely proportional to the idle current in the output stage — very low idle current results in very high output impedance.)</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Input bias current —</b> a small amount of current (typically ~10 nA for bipolar FDAs, or picoamperes for CMOS designs) flows into the inputs. This current is mismatched slightly between the inverting and non-inverting inputs (there is an input offset current). This effect is usually important only for very low power circuits.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Input offset voltage — </b>the FDA will produce an output even when the input pins are at exactly the same voltage. For circuits which require precise DC operation, this effect must be compensated for.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Common mode gain —</b> A perfect operational amplifier amplifies only the voltage difference between its two inputs, completely rejecting all voltages that are common to both. However, the differential input stage of an FDA is never perfect, leading to the amplification of these identical voltages to some degree. The standard measure of this defect is called the common-mode rejection ratio (denoted, CMRR). Minimization of common mode gain is usually important in non-inverting amplifiers (described below) that operate at high amplification.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Temperature effects —</b> all parameters change with temperature. Temperature drift of the input offset voltage is especially important. </span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><b><span lang="EN-US">AC imperfections</span></b></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Finite bandwidth —</b> all amplifiers have a finite bandwidth. This is because FDAs use internal frequency compensation to increase the phase margin.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Input capacitance —</b> most important for high frequency operation because it further reduces the open loop bandwidth of the amplifier.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Common mode gain — </b>See DC imperfections, above.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Noise -</b> all real electronic components (except superconductor) generate noise. You can find devices with 0.8 to several hundreds nv/rtHz noise performance. </span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><b><span lang="EN-US">Nonlinear imperfections</span></b></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Saturation —</b> output voltage is limited to a peak value, usually slightly less than the power supply voltage. Saturation occurs when the differential input voltage is too high for the op-amp's gain, driving the output level to that peak value.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Slewing —</b> the amplifier's output voltage reaches its maximum rate of change. Measured as the slew rate, it is usually specified in volts per microsecond. When slewing occurs, further increases in the input signal have no effect on the rate of change of the output. Slewing is usually caused by internal capacitances in the amplifier, especially those used to implement its frequency compensation, particularly using pole splitting.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Non- linear transfer function —</b> The output voltage may not be accurately proportional to the difference between the input voltages. It is commonly called distortion when the input signal is a waveform. This effect will be very small in a practical circuit if substantial negative feedback is used. </span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b>Power considerations</b></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Limited output power — </b>if high power output is desired, an op-amp specifically designed for that purpose must be used. Most op-amps are designed for low power operation and are typically only able to drive output resistances down to 2 k</span>Ω<span lang="EN-US">.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b> * Limited output current — </b>the output current must obviously be finite. In practice, most op-amps are designed to limit the output current so as not to exceed a specified level thus protecting the FDA and associated circuitry from damage. </span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"> <b>DC behavior</b></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US">Open-loop gain is defined as the amplification from input to output without any feedback applied. For most practical calculations, the open-loop gain is assumed to be infinite; in reality it is obviously not. Typical devices exhibit open-loop DC gain ranging from 100,000 to over 1 million; this is sufficiently large for circuit gain to be determined almost entirely by the amount of negative feedback used. Op-amps have performance limits that the designer must keep in mind and sometimes work around. In particular, instability is possible in a DC amplifier if AC aspects are neglected.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US"><b>AC behavior</b></span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US">The FDA gain calculated at DC does not apply at higher frequencies. To a first approximation, the gain of a typical FDA is inversely proportional to frequency. This means that an FDA is characterized by its gain-bandwidth product. For example, an FDA with a gain bandwidth product of 1 MHz would have a gain of 5 at 200 kHz, and a gain of 1 at 1 MHz. This low-pass characteristic is introduced deliberately, because it tends to stabilize the circuit by introducing a dominant pole. </span>This is known as frequency compensation.</span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><span style="font-size: small;"><span lang="EN-US">Typical low cost, a general purpose FDA exhibits a gain bandwidth product of a few megahertz. Specialty and high speed FDAs can achieve gain bandwidth products of hundreds of megahertz. Some FDAs are even capable of gain bandwidth products greater than a gigahertz.</span></span></div><div class="MsoNormal" style="font-family: Verdana,sans-serif; line-height: normal; margin-bottom: 0.0001pt; text-align: justify;"><br />
</div><span style="font-size: x-small;"><span style="font-family: verdana, sans-serif;">Hernández Caballero Indiana</span><br style="font-family: verdana,sans-serif;" /><span style="font-family: verdana, sans-serif;">Asignatura: CAF</span><br style="font-family: verdana,sans-serif;" /> <span style="font-family: verdana, sans-serif;">Fuente:<a href="http://www.reference.com/browse/Fully_differential_amplifier">http://www.reference.com/browse/Fully_differential_amplifier</a> </span></span></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-74485467430514313172010-06-25T20:06:00.002-04:302010-06-27T19:17:38.324-04:30DISEÑO Y SIMULACIÓN DE UN AMPLIFICADOR OPERACIONAL COMPLETAMENTE DIFERENCIAL EN TECNOLOGÍA CNM25<h3 class="post-title entry-title"><a href="http://indianamaithe.blogspot.com/2010/06/diseno-y-simulacion-de-un-amplificador.html"></a> </h3><div class="post-header"></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"> <b>INTRODUCCIÓN</b><br />
<br />
Los circuitos integrados analógicos de alto rendimiento hacen uso cada vez más frecuente de amplificadores operacionales con salida diferencial. Esto se debe a las excelentes características de rechazo de fuente y de ruido que presentan, debido a la naturaleza diferencial del circuito1.<br />
<br />
Sin embargo, este tipo de amplificadores debe tener un circuito de realimentación, conocido como Circuito de Realimentación de Modo Común (CMFB, Common Mode Feedback Circuit) que establezca las tensiones de salida de modo común en un valor estable. Existen diversas alternativas para la implementación de este circuito, tales como resistores, pares diferenciales y circuitos de capacitores conmutados.<br />
<br />
Se presenta en este trabajo el diseño de un amplificador operacional completamente diferencial en la tecnología CNM25 del Centro Nacional de Microelectrónica (CNM) de España. La simulación del circuito arroja una ganancia diferencial (Ad) de 81 dB con un ancho de banda de ganancia unitaria (GBW) de 8.69 Mhz. La ganancia en modo común se redujo a –31 dB mediante la implementación de un circuito CMFB (en tiempo continuo) de par diferencial.<br />
<br />
<b>DESCRIPCIÓN DEL CIRCUITO</b><br />
<br />
El circuito del operacional se muestra en la fig. 1, donde el CMFB se incluye como bloque por razones de claridad. Se trata de una topología cascodo plegado clásica completamente diferencial. Se pretende obtener una ganancia Ad de 80 dB y un GBW de 7MHz, con una alimentación de +2.5 voltios y -2.5 voltios.<br />
<br />
Para tal fin los transistores M1 y M2 se polarizan a valores bajos de tensiones efectivas (Vef = Vgs – Vt = 0.25 voltios) para aumentar sus transconductancias y consecuentemente la ganancia Ad y el GBW.<br />
Se proponen para los transistores M3 a M7 valores elevados de Vef (Vef = 0.5 voltios), con el propósito de reducir la variación de las corrientes circulantes debido a fluctuaciones estadísticas en la tensión de umbral delos transistores.<br />
<br />
Los transistores M8 a M11 presentan valores más bajos de Vef para elevar sus transconductancias y consecuentemente, por efecto cascodo, el valor de la impedancia de salida de circuito5 (Vef8 = Vef9 = 0.25 voltios, Vef10= Vef11= 0.2 voltios).<br />
<br />
Adicionalmente debe mencionarse que se establece para M4 a M7 una tensión drenador-surtidor de 200mv por arriba de las tensiones de saturación para maximizar la excursión de salida del amplificador.<br />
<br />
El circuito CMFB se muestra en la fig. 2. El mismo es de funcionamiento en modo continuo y basado en dos amplificadores de par diferencial. Este circuito balancea las tensiones de salida del amplificador (Vo+ y Vo-) de manera tal que la tensión en modo común siga una referencia establecida (0 voltios en este trabajo).Para tal fin provee una salida (Vctrl) que se utiliza para controlar las fuentes de corriente M6 y M7 de la fig. 1. El lazo de realimentación así formado estabiliza el modo común a la salida del amplificador.</span><br />
<br />
</div><div style="font-family: Verdana,sans-serif; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiCcHs7mek3Ncxm9K3bhVaGVrxNFgnpSVI9qMQOGQhDypae3UW1fYnKLvgnYzc4CtxY1mBvIBqvfAkWRNjcbcdjUc2ofeWyq1XQQbJWO5y03vehSGdzgOnIWghv8qUUZ73STyw3-ncpiqY/s1600/Dibujo1.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="277" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiCcHs7mek3Ncxm9K3bhVaGVrxNFgnpSVI9qMQOGQhDypae3UW1fYnKLvgnYzc4CtxY1mBvIBqvfAkWRNjcbcdjUc2ofeWyq1XQQbJWO5y03vehSGdzgOnIWghv8qUUZ73STyw3-ncpiqY/s400/Dibujo1.bmp" width="400" /></a></div><span style="font-size: small;">Una dificultad que presenta el CMFB propuesto es la severa limitación que produce en la excursión de la tensión de salida del amplificador debido a un rango dinámico reducido en las entradas del CMFB. Para disminuir este efecto se deben elegir tensiones efectivas grandes para los transistores M1f a M4f de la fig. 2. <br />
<br />
Sin embargo, esta elección disminuye la ganancia del CMFB, la cual depende de la relación de transconductancia de M1f a M5f, debiéndose compensar mediante un aumento en la corriente de polarización. Consecuentemente los valores de polarización resultan de un compromiso entre los aspectos antes citados (ganancia y excursión).<br />
<br />
Para este trabajo se propone una Vef de 0.8 voltios para M1f a M4f y una corriente de 15 uA. La tensión efectiva de M5f y M6f está determinada por la polarización de M6 y M7 de la fig. 1. Para las fuentes de corriente M7f y M8f se siguen las mismas consideraciones que para M4 y M5.<b> </b></span><br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiCcHs7mek3Ncxm9K3bhVaGVrxNFgnpSVI9qMQOGQhDypae3UW1fYnKLvgnYzc4CtxY1mBvIBqvfAkWRNjcbcdjUc2ofeWyq1XQQbJWO5y03vehSGdzgOnIWghv8qUUZ73STyw3-ncpiqY/s1600/Dibujo1.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="277" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiCcHs7mek3Ncxm9K3bhVaGVrxNFgnpSVI9qMQOGQhDypae3UW1fYnKLvgnYzc4CtxY1mBvIBqvfAkWRNjcbcdjUc2ofeWyq1XQQbJWO5y03vehSGdzgOnIWghv8qUUZ73STyw3-ncpiqY/s400/Dibujo1.bmp" width="400" /></a></div><br />
<span style="font-size: small;"><b>RESULTADOS</b><br />
<br />
Los resultados se obtienen mediante simulación Spice con los modelos provistos por el CNM.<br />
<br />
Las corrientes de polarización de los transistores M3a M5(fig.1) se establecen en 160 uA y las de M1, M2 y M6 a M11 en 80 uA. En el circuito CMFB, M1f a M4f (fig.2) se polarizan a 15 uA y M5f a M8f a 30 uA.<br />
<br />
Las excursiones de salida máximas del circuito pueden verse en la fig. 3, las cuales se determinan mediante un barrido de DC a las entradas del amplificador en condición de ganancia unitaria para modo diferencial. La salida puede excursionar entre 0.84 voltios y –2.13 voltios, lo que evidencia el efecto de reducción del rango dinámico por efecto del CMFB, tal cual se expresa anteriormente en este trabajo.<br />
<br />
La respuesta en frecuencia en modo diferencial se muestra en la fig. 4, en la cual se observa que la ganancia es de 81 dB con un GBW de 8.69 MHz. En modo común (fig.5) se obtiene una ganancia de –30.85 dB. La respuesta en frecuencia de la ganancia de lazo de realimentación de modo común se muestra en la fig. 6, con 31 dB de ganancia y un GBW de 1.07MHz.<br />
<br />
La respuesta temporal del amplificador se evalúa configurando el circuito como muestra la fig. 7. Se simulan cuatro condiciones de carga capacitiva y se determina la velocidad de crecimiento para cada caso. Los resultados se muestran en la tabla 1 y en la fig. 8.<b> <br />
<br />
</b></span></div><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEigiY7iTUtDo443HhCExA8bBzC4TLFNioqk_mE-jMLTqZzS71tr7iJ9RwYFQdEs_F_HPjBhR9nChFa0CmDmVYtaXBPrtlg8eeGvTXxja1kcSkcUIgMdXxEN-a8b_mD4gI1AxmY6_LVVciU/s1600/Dibujo2.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="172" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEigiY7iTUtDo443HhCExA8bBzC4TLFNioqk_mE-jMLTqZzS71tr7iJ9RwYFQdEs_F_HPjBhR9nChFa0CmDmVYtaXBPrtlg8eeGvTXxja1kcSkcUIgMdXxEN-a8b_mD4gI1AxmY6_LVVciU/s400/Dibujo2.bmp" width="400" /></a></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjTDvi3ql9wxlHP69WxHExUunYPZvszEkT0C06-nQZ1mQudUr5yaQ287LyWcva5pp_CgdvExLnbK9_vWoVuQSQUkI4Xmo6pdKA5Leh5NyL7smSTwXmHKNUOSnYOSqOqCe9OIUxZgRhrJ0Q/s1600/Dibujo3.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="191" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjTDvi3ql9wxlHP69WxHExUunYPZvszEkT0C06-nQZ1mQudUr5yaQ287LyWcva5pp_CgdvExLnbK9_vWoVuQSQUkI4Xmo6pdKA5Leh5NyL7smSTwXmHKNUOSnYOSqOqCe9OIUxZgRhrJ0Q/s400/Dibujo3.bmp" width="400" /></a><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh1lPBW9570Vk1_aoxrJ2dykBjeOXCJcvl2O2f77yXBfCyI9WsF9GTXd0Imx-gKwUrkJIGZNtXptjGlJ22KpLLVYlep5tBlSi0SDXJU11RPvtNd8Hl7fP09VqJSiYGw9F-JnKp1SejYJCg/s1600/Dibujo4.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="173" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEh1lPBW9570Vk1_aoxrJ2dykBjeOXCJcvl2O2f77yXBfCyI9WsF9GTXd0Imx-gKwUrkJIGZNtXptjGlJ22KpLLVYlep5tBlSi0SDXJU11RPvtNd8Hl7fP09VqJSiYGw9F-JnKp1SejYJCg/s400/Dibujo4.bmp" width="400" /></a></div><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_elz1nIyiCYGfFHR2nottGkMUt42tEmzPiigB2HLQlMlXTqbNvTKge7r8wW7puUoa6QFPxbm1o-04l8pzOe7ExoBcaEclWcGxzSZkq9FfLXutetnpCRTmtgi1Tw7AzZIK4T-Q5sIAMNk/s1600/Dibujo5.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="181" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEg_elz1nIyiCYGfFHR2nottGkMUt42tEmzPiigB2HLQlMlXTqbNvTKge7r8wW7puUoa6QFPxbm1o-04l8pzOe7ExoBcaEclWcGxzSZkq9FfLXutetnpCRTmtgi1Tw7AzZIK4T-Q5sIAMNk/s400/Dibujo5.bmp" width="400" /></a></div><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjHV-_l4N_o7phimYjN5svtksIhUVjnJ7k9RqjTYp8c49ztynUcQfgYoLJvEQQVI_PkO7h28A82hAa9dBNnyBW4bUlR6YI16IX7Pm0m1yjbtMOfN3Gl-DwHPUvQSxpxFMEblFH5J_d1RpU/s1600/Dibujo7.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="183" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEjHV-_l4N_o7phimYjN5svtksIhUVjnJ7k9RqjTYp8c49ztynUcQfgYoLJvEQQVI_PkO7h28A82hAa9dBNnyBW4bUlR6YI16IX7Pm0m1yjbtMOfN3Gl-DwHPUvQSxpxFMEblFH5J_d1RpU/s400/Dibujo7.bmp" width="400" /></a></div><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnPy3qtQlYFLnE1uqfGdTzVa8AzMAdJDXbw97y-D3evQ4G38FV0FtYrH045P-nzsq1iujLtMcOoTwiOMIddHZ4EZKx13z8kjb6SsVAWqVmRMz_Bf20WwCiIuc5WLDq6E5N7px7xE3cSv0/s1600/Dibujo6.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="131" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhnPy3qtQlYFLnE1uqfGdTzVa8AzMAdJDXbw97y-D3evQ4G38FV0FtYrH045P-nzsq1iujLtMcOoTwiOMIddHZ4EZKx13z8kjb6SsVAWqVmRMz_Bf20WwCiIuc5WLDq6E5N7px7xE3cSv0/s320/Dibujo6.bmp" width="320" /></a></div><br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiLzkSftViNJsru-JWJf_8wVbF-eaWw7VdkHBzY3Gpd05ILUFYcPKSjAnbTnrtiZJScvmNXa4STgA2wT_Klvmmupe33RRCm7TodxE1Z2mwtv73IxJC1dOhdbUOmz9eLqHUpUxH9FBjk5-w/s1600/Dibujo8.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="177" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEiLzkSftViNJsru-JWJf_8wVbF-eaWw7VdkHBzY3Gpd05ILUFYcPKSjAnbTnrtiZJScvmNXa4STgA2wT_Klvmmupe33RRCm7TodxE1Z2mwtv73IxJC1dOhdbUOmz9eLqHUpUxH9FBjk5-w/s400/Dibujo8.bmp" width="400" /></a></div><br />
<span style="font-size: small;"><b>CONCLUSIONES<br />
<br />
</b></span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">En este trabajo se presenta el diseño y simulación de un amplificador operacional completamente diferencial con circuito CMFB de tiempo continuo en la tecnología CNM25 de 2.5 micrones.<br />
<br />
El CMFB logra una reducción de la ganancia en modo común sin penalización apreciable de la ganancia Ad. Sin embargo debe mencionarse el gran impacto del CMFB sobre la excursión de salida, que se ve deteriorada, constituyendo éste el mayor inconveniente presentado por este circuito.<br />
<br />
Como desafío futuro se plantea el desarrollo de un CMFB que permita mayores excursiones, tales como del tipo Push-Pull</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">Hernández Caballero Indiana<br />
Asignatura: CAF<br />
Fuente:<a href="http://www.iberchip.org/VII/cdnav/pdfp/p12.pdf">http://www.iberchip.org/VII/cdnav/pdfp/p12.pdf</a> <br />
</span></div>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0tag:blogger.com,1999:blog-1622471101183667918.post-37277761388611758002010-06-25T20:01:00.002-04:302010-06-27T19:17:17.832-04:30Rechazo de Modo Común en Amplificadores de Instrumentación<h3 class="post-title entry-title"><a href="http://indianamaithe.blogspot.com/2010/06/rechazo-de-modo-comun-en-amplificadores.html"></a> </h3><div class="post-header"></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><b>Introducción</b><br />
<br />
Existen en equipos en la industria, en equipos de electromedicina, y en equipos en otras muchas aplicaciones, la necesidad de medir señales muy pequeñas del orden de microvoltios o pocos milivoltios en la presencia de comparativamente grandes señales de ruido provenientes de distintas fuentes, como ser motores, tubos de iluminación de descarga gaseosa, y la siempre presente inducción de la frecuencia de línea de alimentación, en nuestro caso 50Hz. Para realizar las mencionadas mediciones estos deberán utilizar en su entrada Amplificadores de Instrumentación con un adecuada Relación Rechazo de Modo Común (CMRR).<br />
<br />
En la siguiente figura se coloca un esquema básico de medición </span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"><br />
</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhePq-WWPey6fW0OwcG_YeGAxtYfXpzCFt8ZPm8PDuyi8T8Az9BZAE9rGGX46cmAUPyHEpgAT1FVGRb5iGzKj2YeNKSnTvpUj-qFwSU4IiRaFh-iNK3fRBGFkB1_EMW3Cgf2BthvPR_23o/s1600/Dibujo.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" height="206" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhePq-WWPey6fW0OwcG_YeGAxtYfXpzCFt8ZPm8PDuyi8T8Az9BZAE9rGGX46cmAUPyHEpgAT1FVGRb5iGzKj2YeNKSnTvpUj-qFwSU4IiRaFh-iNK3fRBGFkB1_EMW3Cgf2BthvPR_23o/s400/Dibujo.bmp" width="400" /></a></div><span style="font-size: small;"><br />
</span><br />
<span style="font-size: small;">Al Amplificador de Instrumentación ingresan dos señales de modo común: una de c.c. de +2.5V provenientes del puentes de resistencias y otra de c.a. Vruido inducida sobre los cables de entrada al amplificador.-<br />
<br />
<b>Rechazo de Modo Común</b><br />
<br />
Los amplificadores de Instrumentación amplifican la diferencia entre dos señales. Esas señales diferenciales en la práctica provienen de sensores como ser termocuplas, fotosensores, puentes de medición resistivos, etc. En la figura de arriba se ve que de un puente resistivo, en estado de equilibrio sin señal, en la mitad de las ramas del puente existe una señal de 2.5V respecto a masa. Esta señal de corriente continua es común a ambas entradas por lo cual es llamada Voltage de Modo Común de la señal diferencial. Se puede ver que estas señales no contienen información útil en lo que se quiere medir y como el amplificador amplificará la diferencia de ambas, al ser igulaes, se restan y a la salida el resutado será cero o sea idealmente no están contribuyendo a la información de salida. También se ve que se inducen señales de corriente alterna en ambas entradas a la vez y que serán rechazadas como en el caso de continua. Pero al producirse un desbalance del equilibrio del puente por la variación de una de sus resistencias se producirá una señal que será aplicada entre ambas entradas y será amplificada. Por lo expuesto, es que se justifica la utilización de amplificadores de instrumentación para rechazar señales que entran en modo común, osea en las dos entradas se presenta la misma señal.<br />
<br />
En la práctica, las señales de modo común nunca serán rechazadas completamente, de manera que alguna pequeña parte de la señal indeseada contribuirá a la salida.</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><br />
</div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"></span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">Para cuantificar la calidad del Amplificador de Instrumentación, se especifica la llamada Relación de Rechazo de Modo Común (CMRR) que matemáticamente se expresa como:</span><br />
<br />
<div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhmxqgB6YzOlWynqOMasWHHXq6fa_9qeP8sPxi0xjDMVGRphqEhQ3DSxPcBQcIK9sf4oWxafwTOjaGSZ5uXmRisCNB7icNwmlND-JFYEsQHFEtOV8zb-S-AZcuqIPXPwJAdbtfUPoExeVw/s1600/Dibujo2.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhmxqgB6YzOlWynqOMasWHHXq6fa_9qeP8sPxi0xjDMVGRphqEhQ3DSxPcBQcIK9sf4oWxafwTOjaGSZ5uXmRisCNB7icNwmlND-JFYEsQHFEtOV8zb-S-AZcuqIPXPwJAdbtfUPoExeVw/s320/Dibujo2.bmp" /></a></div></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"></span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">siendo:<br />
<br />
* AD= Amplificación Diferencial<br />
* AD = Vout / Vin diferencial<br />
* ACM= Amplificación Modo Común<br />
* VCM= Voltage de modo común en la entrada<br />
* ACM = Vout / VCM<br />
* Vout= Voltage de salida<br />
<br />
De la última fórmula podemos obtener la Vout como:</span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"></span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhoj97bI5deowMMBvyEzmJ0Zdb84bsPHKMA9IF7bseCL28BudLjhz_Zop-ypSf65U4JMSg54ocuWE35R8wRf5vxL2lg_-gjC7fGHTGqeRY8oECJ0RXE24q9EATOB5WgTASgIv-9mFtqZvU/s1600/Dibujo3.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEhoj97bI5deowMMBvyEzmJ0Zdb84bsPHKMA9IF7bseCL28BudLjhz_Zop-ypSf65U4JMSg54ocuWE35R8wRf5vxL2lg_-gjC7fGHTGqeRY8oECJ0RXE24q9EATOB5WgTASgIv-9mFtqZvU/s320/Dibujo3.bmp" /></a></div><br />
</div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">De las hojas de datos de los Amplificadores de Instrumentación podemos obtener por ejemplo<br />
<br />
* CMRR=100db ;<br />
* AD =10 ;<br />
* De la figura, VCM de modo común es de 2.5Volt<br />
<br />
de donde:<br />
<br />
Vout = 250uV para el caso de la figura anterior. <br />
<br />
<b>Rechazo de Modo Común de c.a. y de c.c.</b><br />
<br />
Como se ve en la figura de arriba, y como se dijo, se presentan a las entradas diferenciales, señales de c.c. y de c.a. y al no ser infinito el CMRR, una cierta cantidad de ambas estarán presentes en la salida, además de la señal diferencial deseada. La componente indeseada de c.c. puede considerarse como un offset y es sencillo ajustarlo externamente. La componente indeseada de c.a. es más complicada de disminuir a la entrada, y se hace principalmente utilizando filtros de c.a. colocados en la entrada, disminuyendo el ancho de banda de utilización del amplificador.<br />
<br />
La especificación de CMRR en función de la frecuencia se obtiene de las hojas de datos. En la figura siguiente se puede apreciar como varía el CMRR, disminuyen a medida que aumenta la frecuencia.</span><br />
<br />
</div><div style="font-family: Verdana,sans-serif; text-align: justify;"><div class="separator" style="clear: both; text-align: center;"><a href="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj7G9dmhpBzWBqKTKvEFWG6fObFCESG_JqUzcnUPLvjuMhaBapCFwMwa0f57HF4Ga2dabLDRZ50LEilyO8JYEQ4zu2FDyVTMGykVBoLvuXVBVHTuXjwNJGCisM4Jin4gbf-hR0zmNR6ZI4/s1600/Dibujo4.bmp" style="margin-left: 1em; margin-right: 1em;"><img border="0" src="https://blogger.googleusercontent.com/img/b/R29vZ2xl/AVvXsEj7G9dmhpBzWBqKTKvEFWG6fObFCESG_JqUzcnUPLvjuMhaBapCFwMwa0f57HF4Ga2dabLDRZ50LEilyO8JYEQ4zu2FDyVTMGykVBoLvuXVBVHTuXjwNJGCisM4Jin4gbf-hR0zmNR6ZI4/s320/Dibujo4.bmp" /></a></div><br />
</div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;"></span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><span style="font-size: small;">La respuesta en frecuencia del CMRR es plana hasta alrededor de 100 HZ </span></div><div style="font-family: Verdana,sans-serif; text-align: justify;"><br />
</div><span style="font-size: x-small;"><span style="font-family: verdana, sans-serif;">Hernández Caballero Indiana</span><br style="font-family: verdana,sans-serif;" /><span style="font-family: verdana, sans-serif;">Asignatura: CAF</span><br style="font-family: verdana,sans-serif;" /> <span style="font-family: verdana, sans-serif;">Fuente:<a href="http://www.huarpe.com/electronica/ao1/aoicmrr1.html">http://www.huarpe.com/electronica/ao1/aoicmrr1.html</a></span></span>Tecnología en Telecomunicaciones - conocimientos.com.vehttp://www.blogger.com/profile/13517798918797491823noreply@blogger.com0