A Fully Differential Wide-Band Operational Amplifier

A Fully Differential Wide-Band Operational Amplifier

DESIGN SPECIFICATIONS AND INITIAL DECISION
A fully differential wide-band operational amplifier is designed for a 1st-order RC low-pass filter. The low-pass filter
and specifications are shown in Fig. 1 and Table I. The output is used to drive an identical stage. Given the low load
resistance (R1 = 2k­), we realized that using a single-stage amplifier is impossible to achieve a reasonably high gain
(for example, DC gain of 594 is required to reach 1% error on the closed loop gain). Thus, a two-stage structure is
mandatory. Initially, we design the first stage to be a fully differential pairs with active load, which provides most of
the required gain. The second stage is a simple common source stage which provides large output swing and additional
gain. The detailed analysis is presented in the next section.

ANALYSIS UNDER IDEAL CONDITIONS
We model the operational amplifier as a voltage-controlled voltage source with finite gain. The diagram is shown in
Figure 2. The open loop voltage gain is A, output resistance Ro. We want to find the conditions on A and Rout to
satisfy the gain requirement.
A. Loaded Gain and Output Resistance
Since this is a shunt-shunt feedback, it is convenient to convert the input voltage source into an input current source
and compute the transimpedence Ro. We break the feedback loop in Fig. 3. First, we ignore all the capacitance to
compute the DC gain.
B. Dominant Pole
In order to satisfy the 3-dB bandwidth requirement, we want to compute the dominant pole of the close loop system
and find the conditions on the open loop gain A and bandwidth. This can be done by including capacitance in the
previous calculation.
C. Phase Margin
Two-stage amplifier has two proximate dominant poles at the outputs of both stages. Proper compensation is needed to
obtain a 60± phase margin. In our design, this is done by adding a capacitor C0 and a resistor R0 between the outputs
of the two stages. Adding C0 splits the two low frequency poles. Inserting R0 introduces a left half plane (LHP) zero
to help prevent the phase drop at low frequency. The exact value of the compensation capacitance is decided through
simulations. The frequency of zero is finely tuned so that it is located near the second pole, and this gives rise to the
best possible phase margin. Again, this is done through parametric simulation with Cadence.

SIMPLE DIFFERENTIAL AMPLIFIER
A. Design Summary
The main circuitry of a simple two-stage amplifier is shown in Fig. 4. The compensation circuitry consists of R0 and
C0. The gate of M2 and M3 are controlled by the bias circuitry, and the gate of M11 is connected to the output of
common mode feedback circuitry. The bias currents for the first and second stages are 0.6mA and 1.92mA respectively.
The relatively high current is due to the high bandwidth requirement. This places a stringent condition on the amplifier
pole locations. The bias circuitry is shown in Fig. 5. A ideal current source is used. Wire vg2, vg26, and vg15 are
connected to the gate of M2, M26, and M15. The common mode feedback circuit uses differential pairs, as shown
in Fig. 6. The differential outputs of the amplifier are connected to vg21 and vg24. Wire vg11 is routed to the gate
of M11, which controls the tail current of the different pair at first stage. The common mode voltage vcm is set to
0.9V using a ideal voltage source. Caution is needed in sizing transistors M21»M24. Their overdrive voltages should
be high enough such that the different pairs in common mode feedback circuitry remain on for the entire differential
output range. In order to minimize the power dissipation, the bias current in common mode feedback is kept low by
adjusting the transistor sizes.
B. Simulation
The transistor sizes, DC current, and small signal parameters (gm; vsat) are listed in Table II. The channel lengths of
transistors on the second stage are minimized 0:18¹mbecause the load resistor dictates the gain on the second stage.
The channel lengths of the transistors on the first stage is determined by the tradeoff between gain and bandwidth
(phase margin). Increasing channel length leads to higher gain but introduces more capacitance on the intermediate
output. We will have more on these tradeoffs in the discussion section. The circuit was simulated and the result
is reported in Table III. The output with a full 1.72V swing is shown in Fig. 7, when the input was a sinusoid at
2MHz. The 3rd harmonics distortion is obtained using the discrete Fourier transform. While all other requirements
are satisfied, we only reach a close loop bandwidth of 9.724 MHz. We conceive that increasing the current on the
second stage may lead to a better result, but we did not pursue further on the direction. Table III also includes the
result of a design using telescopic cascode at the first stage, which we will discuss in the next section.

CASCODED DIFFERENTIAL AMPLIFIER
In the previous design, we used a simple differential pair as the first stage. Since the cascode structure can achieve
higher gain, it is interesting to see if power dissipation can be improved by using this structure. We also implemented
a cascode differential pair design. The main circuitry and bias circuitry are given in Fig. 8 and Fig. 9 respectively. In
this high swing bias circuitry, transistor M31 is design to be in triode region, and it sets the Vds of M2 and M3. Bias
vg20 needs to be appropriately chosen such that M19 and M20 work in saturation region. The corresponding transistor
sizes and their operational conditions are listed in Table IV. The common mode feedback is the same as the previous
one as shown in Fig. 6, so we choose not to list their transistors.
The best result we got is presented in Table III. Although using a cascode at the first stage helps enhance the gain
substantially, the bandwidth becomes slight worst than our previous design. This is understandable since the dominant
pole in the cascode design is located at lower frequency than the simple design.

DISCUSSION
In this section we discuss the tradeoffs involved in adjusting the designing parameters such as the device sizes and bias
current when the simple design in section III is used. The results are summarized in Table V. We use gm1 and gm2
to denote the transconductance of the first and second stages. p1 and p2 indicate the dominant and secondary poles.
Rout1 and Rout2 mean the output resistances of first and second stages.

http://www.ee.ucla.edu/~huiyu/reports/ee215a.pdf

Danny Camperos   CRF

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