Proposed frequency doubler: Fig. 1 shows the proposed frequency doubler, which is designed with a stacked push–push configuration using N- and P-MOS transistors to generate differential output. In Fig. 1, the large resistors RB are included for DC biasing which makes no additional DC bias necessary. The output loads at nodes A and B are implemented with inductors considering the low supply voltage of 1.25 V.
The direct-conversion up-mixer shown in Fig. 2 has been fabricated based on 0.25 mm CMOS technology. Fig. 3 shows the microphotograph of the fabricated chip. The chip area is 0.5 mm2. In the measurement, 10 MHz IF signal and 450 MHz LO signal are applied to the up-mixer. The measured up-mixer shows 5.5 dB of power conversion gain, 7.5 dBm of output IP3, and 40 dB rejection to the fundamental LO signal, while dissipating 4.5 mA from 1.25 V supply. Of the total current, the frequency doubler dissipates 1 mA. The IP3 behaviour of the designed up-mixer is shown in Fig. 4.