A CMOS Single Stage Fully Differential OP-Amp with 120 dB DC Gain

A CMOS Single Stage Fully Differential
OP-Amp with 120 dB DC Gain

INTRODUCTION
n many analog circuit applications such as A/D
converters [1], switched capacitor filters [2] and sampleand-
hold amplifiers, speed and accuracy are determined by
the settling behavior of the op amp circuit. The settling
speed mainly depends on the unity gain frequency and a
single pole settling time while high settling accuracy is due
to high DC gain of the op-amp circuit [3].
In order to achieve both high settling speed and high DC
gain, several circuit approaches such as dynamic biasing of
trnsconductance amplifier [4], triple-cascode amplifier [5],
positive-feedback transconductance amplifier [6] were
proposed, but the gain and unity gain frequency of those
gain boosting techniques are not enough for the recent
submicron CMOS circuit applications. In 1990, K. Bult and
G. Geelen proposed the folded cascode op-amps with the
gain boosting technique [7], which shows a DC gain of 90
dB and a unity-gain frequency of 116MHz with 16pF load.
The gain boosting technique is introduced by Hosticka in
1979[8] and Bult and G. Geelen firstly applied this
technique to op-amp.
Based on the folded cascode op-amp design with the gain
boosting technique, this paper presents the state-of-the-art
120dB DC gain fully differential op-amp with 381MHz
unity gain frequency using IBM 0.25μm CMOS
technology.
The gain boosting technique is explained in section II
and the circuit's frequency behavior is analyzed in section
III. In section IV, the circuit implantation with 0.25 CMOS
process is presented. The simulation results are given and
discussed in section V.

GAIN BOOSTING
As shown in Figure 1, the idea of gain boosting is based
on negative feedback loop to set the drain voltage of M2
[9]. Negative feedback drives the gate of M2 until Vx has
the same value as Vref. Therefore, the variation of Vout has
much less effect on VX, because Aadd "regulates" this
voltage. This topology is usually called "regulated
cascode" or "active cascode". With the smaller variation of
VX due to the change of Vout, the output current becomes
less sensitive to the voltage variation at Vout compared with
conventional cascode structure.
This increased output resistance results in several orders
of improvements on the overall gain.
FREQUENCY ANALYSIS
A. Differential Folded Cascade Op Amp
For a fully differential folded cascode op amp like the
one shown in Figure2, the dominant pole is the pole at
output node (node B) which has the highest impedance and
in most cases, the highest capacitance.
The second pole is at the cascade transistor source node.

Regulated Folded Cascade Op Amp
As discussed in session II, additional amplifier stages are
used to boost gain [7]. Figure 3 shows the half circuit of the
proposed op amp.
With the addition of the gain boost amp, the second pole
frequency is changed. The source-gate capacitance of M2
now forms a Miller cap which is connected between the
input and output of the additional amp B. Therefore the
capacitance seen at node A is not just Cgs2 now, but
(1+AB)Cgs2 where AB is the gain of the additional amp B.
This reduces the second pole frequency wp2 and thus
degrades the phase margin of the op amp. In order to
overcome this effect, an extra cap is added at the output of
amp B. The extra cap reduces the dominant pole frequency
of amp B so that its gain drops to a much lower value
around wp2. This reduces the Miller effect and pushes up
the second pole frequency.
A schematic of this technique is shown in Figure 4 and
the simulated bode and phase plots with and without the
extra cap are shown in Figure 5. It is shown that without
the extra cap, the second pole effect is kicking in around
300MHz which is the unity-gain frequency of the designed
op amp. By adding the extra cap (1pF in this case), the
second pole is pushed up. This effect is shown more clearly
form the phase plot.
For stability concern, the unity gain frequency of the
additional stage (gm /Cladd) has to be larger than the first
pole of the main stage (1/RoutCLmain) [7]. This can be easily
achieved since Rout is typically much larger than 1/gm.

CIRCUIT IMPLENTATION
A. Additional gain stage
The additional gain stages are again implemented
with folded cascade op amps with single end output.
Additional gain stage is applied to both the cascode
transistor and current source of the main stage. NMOS
differential pair is used for amp B (for cascode transistor)
and PMOS differential pair is used for amp A (for current
source). They are chosen based on the common-mode DC
requirement. Low voltage cascode active current mirror is
used in the additional amp. This results in a larger output
DC range and only requires one bias voltage [9]. For
example, Figure 6 shows the schematic of the additional
stage A. Its maximum output voltage is set by Vdd -2VDSAT
which is around 2V.
B. Common Mode Feedback
The common mode feedback is achieved by
controlling the biasing current for the folded cascode in the
main stage. As shown in Figure 7, Current I1 and I2 add up
and go through the current source M5. If Vcm, out gets
higher, current I1 increases and thus current I2 reduces.
This lowers the voltage of node P and as the result, the Ids
of transistor M6, which is the biasing current for the
cascode amp (main stage), increases. This increasing
biasing current will lower down the Vcm, out.
The minimum common mode input is determined by Vdd-
VGS- VDSAT which is about 0.9V. So the common mode
input range is 0.9V-2.5V. This circuit implementation also
allows for the output swing of 0.5-2V. This is basically
determined by the two VDSAT consumed by M1, M2 and
M3, M4 (Figure 2). The dominant pole freq is about 200
Hz and the unity gain frequency of 300 MHz with 2pF
differential load.

SIMULATION RESULTS
Based on the design procedure described in the previous
sections, a single stage 120-dB fully differential op amp
was designed based on IBM 0.25μm CMOS process and
simulated using Cadence Design Systems. As shown in
Figure 8, the entire circuit's chip size is 0.1×0.3 mm2,
which includes the 5 μm wide power supply slab and
ground slab. In this layout, besides the power supply and
ground, only one reference current source are needed to
provide proper biasing for the circuit. The two 1-pf
capacitors were realized using metal-insulator-metal
configuration between layers of Metal 2 and Metal 3. For
the rest part of the circuit, only Metal 1 and Metal 2 were
used in the layout process.
This layout has passed DRC and LVS comparison. In the
simulations, the extracted circuit model based on the layout
has incorporates the layout parasitic capacitances, which
were omitted in the initial schematic simulations. In our
layout, since the device's parasitic capacitances
demonstrate effects similar with the extra capacitors loaded
to the additional stages, the simulated results based on the
extracted circuit model from the layout has a slight higher
unity gain frequency compared with that from the
schematic circuit model. Therefore, only the simulation
results based on the extracted model with parasitic
capacitances are shown in the following discussions. The
capacitor load used in this design at the differential output
is 2pF.